Table of Contents
Advertisement
• Low-side is always the inverse of high-side (PWM_CHANCFG.POLAL through PWM_CHANCFG.POLDL
= 1).
• System uses active high gate driver (PWM_CHANCFG.ENCHOPAH through
PWM_CHANCFG.ENCHOPDH =1).
• Disable gate chopping (PWM_CHANCFG.ENCHOPAL through PWM_CHANCFG.ENCHOPDL =0).
PWM does not use the pulse transformer.
2. Set up the trip and associated interrupt requests using the following bitwise operations on the
and
registers:
PWM_ILAT
PWM_TRIPCFG &= 0xF0F0F0F0
PWM_TRIPCFG |= 0x1010101
PWM_ILAT &= 0xFFE0FFFC
PWM_ILAT |= 0x1
These operations result in the following bit settings:
• All phases must shut down simultaneously in case of fault: (PWM_TRIPCFG.EN0A through
PWM_TRIPCFG.EN0D =0, PWM_TRIPCFG.MODE0A through PWM_TRIPCFG.MODE0D =0,
PWM_TRIPCFG.EN1A through PWM_TRIPCFG.EN1D =0, PWM_TRIPCFG.MODE1A through
PWM_TRIPCFG.MODE1D =0)
• Enable TRIP0 as fault trigger for all channels (PWM_TRIPCFG.EN0A through
PWM_TRIPCFG.MODE1D =1).
• For thermal control and synchronization, SW intervention is needed at trip. Do not use automatic restart
of any channels.
• Generate an interrupt at trip on TRIP0 (PWM_ILAT.TMR0PER = 1).
3. Configure the PWM channels using the following bitwise operations on the
registers:
PWM_CHA_DT=0x32 PWM_CHB_DT=0x32 PWM_CHC_DT=0x32
PWM_TM0 = 0x9C4
PWM_ACTL = 0xFFFFF0000
PWM_BCTL = 0xFFFFF0000
PWM_CCTL = 0xFFFFF0000
PWM_AH0 = 0x0
PWM_BH0 = 0x0
PWM_CH0 = 0x0
These operations result in the following bit settings:
• Configure a dead time of 1 μs (DT =0x32 =0x32)
• Configure a PWM frequency of 20 kHz (assuming a system clock frequency of 100Mhz, so a clock divisor
of 5000:1)
(PWM_TM0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
=0x9C4)
Programming Model for Three-Phase AC Motor Control
PWM_TRIPCFG
PWM_TRIPCFG
and
PWM_ILAT
19–37
Advertisement
Table of Contents
