Analog Devices ADSP-SC58 Series Hardware Reference Manual page 540

Sharc+ processor
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SMPU Functional Description
Table 13-2: ADSP-SC58x SMPU Register List (Continued)
Name
SMPU_IDTLS
SMPU_RADDR[n]
SMPU_RCTL[n]
SMPU_REVID
SMPU_RIDA[n]
SMPU_RIDB[n]
SMPU_RIDMSKA[n]
SMPU_RIDMSKB[n]
SMPU_SECURECTL
SMPU_SECURERCTL[n]
SMPU_STAT
ADSP-SC58x SMPU Interrupts
The SMPU has one interrupt with the SEC ID = 242. See the
rupt Controller (GIC)
chapter for complete information on interrupt generation and use.
Memory Writes
A write transaction to address n is prevented when the following is true.
Address n is in memory region m and memory region m is write-protected (SMPU_RCTL[n].WPROTEN =1) and
ID is not a match. (See
tection and the ID comparison does not result in a match. If an ID comparison results in a match, the write transac-
tion is allowed through.
Memory Reads
A read transaction from address n is prevented when the following is true:
• Address n is in memory region and memory region m is read-protected (SMPU_RCTL[n].RPROTEN =1)
and
• ID is not a match
The block occurs because the memory region is configured for read-protection and the ID comparison does not
result in a match. If the ID comparison results in a match, the read transaction is permitted. (See
13–4
ID
Comparison). The block occurs because the memory region is configured for write-pro-
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Interrupt Details Register
Region n Address Register
Region n Control Register
SMPU Revision ID Register
Region n ID A Register
Region n ID B Register
Region n ID Mask A Register
Region n ID Mask B Register
SMPU Control Secure Accesses Register
Region n Control Secure Accesses Register
SMPU Status Register
System Event Controller (SEC) and Generic Inter-
ID
Comparison).

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