Analog Devices ADSP-SC58 Series Hardware Reference Manual page 899

ADSP-SC58x EPPI Register Descriptions
Table 18-49: EPPI_CTL Register Fields (Continued)
Bit No.
(Access)
11 SIGNEXT
(R/W)
10 IFSGEN
(R/W)
9 ICLKGEN
(R/W)
8 BLANKGEN
(R/W)
7 ITUTYPE
(R/W)
18–60
Bit Name
Sign Extension.
The EPPI_CTL.SIGNEXT select whether (for receive modes when
EPPI_CTL.DLEN selecting 16 bit data length) the data is sign extended or zero fil-
led. Not that EPPI_CTL.SPLTWRD is removed from this shared bit.
Internal Frame Sync Generation.
The EPPI_CTL.IFSGEN bit selects whether the frame syncs are generated internally
or are supplied by an external device.
Internal Clock Generation.
The EPPI_CTL.ICLKGEN bit selects whether the EPPI_CLK is generated inter-
nally or is supplied by an external device.
king Generation (ITU Output Mode).
The EPPI_CTL.BLANKGEN enables ITU output with internal blanking. In GP 8,
10 transmit bit modes (when EPPI_CTL.SPLTWRD is cleared) and 16-, 20-, and
24-bit transmit modes (when EPPI_CTL.SPLTWRD is set),
EPPI_CTL.BLANKGEN selects whether or not the EPPI generates blanking and
generates preamble and insertion with active data from memory.
ITU Interlace or Progressive.
The EPPI_CTL.ITUTYPE selects interlaced or progressive operation for ITU656
mode. This selection is valid for both TX and RX modes.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Zero Filled
1 Sign Extended
0 External Frame Sync
1 Internal Frame Sync
0 External Clock
1 Internal Clock
0 Disable
1 Enable
0 Interlaced
1 Progressive