Table of Contents
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Packet Engine Configuration Register ................................................................................................... 44–58
PE Clock Control Register .................................................................................................................... 44–61
PKTE Continue Register ....................................................................................................................... 44–63
Packet Engine Control Register ............................................................................................................. 44–64
Starting Entry of 256-byte Data Input/Output Buffer ........................................................................... 44–69
Packet Engine Destination Address ........................................................................................................ 44–70
Packet Engine DMA Configuration Register ......................................................................................... 44–71
Packet Engine Endian Configuration Register ....................................................................................... 44–73
Packet Engine Halt Control Register ..................................................................................................... 44–75
Packet Engine Halt Status Register ........................................................................................................ 44–77
Interrupt Mask Disable Register ............................................................................................................ 44–80
Interrupt Mask Enable Register ............................................................................................................. 44–82
Interrupt Masked Status Register ........................................................................................................... 44–84
Packet Engine Input Buffer Count Register ........................................................................................... 44–86
Packet Engine Input Buffer Count Increment Register .......................................................................... 44–87
Interrupt Configuration Register ........................................................................................................... 44–88
Interrupt Clear Register ......................................................................................................................... 44–89
Interrupt Enable Register ...................................................................................................................... 44–91
Interrupt Unmasked Status Register ...................................................................................................... 44–93
Packet Engine Length Register .............................................................................................................. 44–95
Packet Engine Output Buffer Count Register ........................................................................................ 44–97
Packet Engine Output Buffer Count Decrement Register ...................................................................... 44–98
Packet Engine Result Descriptor Ring Base Address .............................................................................. 44–99
Packet Engine Result Descriptor Count Registers ................................................................................ 44–100
Packet Engine Result Descriptor Count Decrement Registers ............................................................. 44–101
Packet Engine Ring Configuration ...................................................................................................... 44–102
Packet Engine Ring Pointer Status ....................................................................................................... 44–103
Packet Engine Ring Status ................................................................................................................... 44–104
Packet Engine Ring Threshold Registers .............................................................................................. 44–105
Packet Engine SA Address .................................................................................................................... 44–107
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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