Analog Devices ADSP-SC58 Series Hardware Reference Manual page 690

Architectural Concepts
Figure 15-9: Enable the Transmitter Before the Receiver
NOTE: Service request interrupts or status are asserted only when the link port (receiver or transmitter) is disabled.
Clocking
The link port clock (LP_CLK) is derived from the internal system clock (CDU0_CLKO4). The link port clock to
system clock ratio can be configured in the
can operate at any asynchronous frequency up to the maximum frequency, independent of the ratio programmed.
The following formula describes the relationship between the frequency of the link port clock, the CDU0_CLKO4
frequency, and the LP_DIV
• f
= f < or = f
LP_CLK SCLK
• f
= f /(2 × DIV) if DIV > 0
LP_CLK SCLK
Where: f = link clock frequency, f
LP_CLK
frequency.
While programming the
exceed the maximum frequency supported for the device. For example, if the CDU0_CLKO4 frequency is 125
MHz and the limit for LP_CLK operation is 83 MHz,
LP_CLK frequency is less than or equal to 83 MHz. For supported frequencies, see the product-specific data sheet.
NOTE: The link ports on this processor have a flexible system clock assignment where their CDU0_CLKO4 is
derived from the CLKO8 output of the CDU. For information on clock programming, see
gramming Model.
Multi-Processor Connectivity
Link ports can operate independently, allowing glueless connection with external processors. Link ports have dedica-
ted DMA channels, allowing independent data transfers. The following group of figures shows some examples of
different bus connection topology that can be used in multi-processor system design. The inter-connection methods
are not limited to these examples.
15–10
LPx_CLK
driven by
transmitter
LPx_CLK held high until
LPx_ACK goes high
LPx_ACK
driven by
receiver
LPx_Dn
BYTE 0
driven by
transmitter
Transmit data held until
LPx_ACK is asserted
LP_DIV
value.
if DIV = 0
LP_CLK-MAX
LP_CLK-MAX
LP_DIV register to select the clock ratio, ensure that the LP_CLK frequency does not
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
LPx_ACK may
deassert after
BYTE 0
BYTE 1 BYTE 2
register. This value applies to the transmitter only. The receiver
= link clock maximum frequency, and f
must be greater than or equal to 1. The resulting
LP_DIV
= system clock
SCLK
CDU Pro-