Analog Devices ADSP-SC58 Series Hardware Reference Manual page 949

Operating Modes
Figure 19-19: ECM Control
Heightened-Precision Edge Placement
Heightened-precision edge placement allows a fine-grained edge placement within the system clock period. The
Heightened-Precision Steps in a Single SCLK Period figure shows how the SCLK0_0 aligned edge is moved to finer
resolution.
Figure 19-20: Heightened-Precision Steps in a Single SCLK0_0 Period
The heightened-precision mode is enabled by setting bits that correspond to the high or low side output option for
the channel in the PWM_CHANCFG
the and
PWM_AH0 PWM_AH1
ed decimal programming is implied for the heightened-precision duty values.
For the PWM_AH output, the duty-cycle register-pair
ed two's complement fixed-point format as shown in the Duty Cycle Notation for Heightened-Precision Edge Place-
ment figure. The weight of bit position at k is 2k.
19–28
+PWM_TM/2
0
COUNT
PWM_AH0=PWM_CH0
PWM_AH
PWM_AL
PWM_BH
2 × DT
PWM_BL
PWM_CH
PWM_CL
1 SCLK PERIOD
AH
AH
HPDUTY
register. bit. The PWM_AH0_HP
registers to provide the overall resolution. The following example explains how sign-
PWM_AH0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
-PWM_TM/2
+PWM_TM/2
0
PWM_AH0=PWM_CH0
2 × DT
and PWM_AH1_HP
and
PWM_AH0_HP
registers work alongside
work together in a Q15.8 sign-