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Previous Initial Descriptor Pointer Register ........................................................................................... 38–61
Status Register ....................................................................................................................................... 38–62
Inner Loop Count Start Value Register .................................................................................................. 38–65
Current Count (1D) or Intra-row XCNT (2D) Register ........................................................................ 38–66
Inner Loop Address Increment Register ................................................................................................. 38–67
Outer Loop Count Start Value (2D only) Register ................................................................................. 38–68
Current Row Count (2D only) Register ................................................................................................. 38–69
Outer Loop Address Increment (2D only) Register ................................................................................ 38–70
Extended Memory DMA (EMDMA)
EMDMA Features ....................................................................................................................................... 39–1
EMDMA Functional Description ................................................................................................................ 39–1
ADSP-SC58x EMDMA Register List ....................................................................................................... 39–2
ADSP-SC58x EMDMA Interrupt List .................................................................................................... 39–2
ADSP-SC58x EMDMA Trigger List ........................................................................................................ 39–3
DMA Addressing...................................................................................................................................... 39–3
DMA Burst Transfers ............................................................................................................................... 39–3
Transfer Control Block (TCB) Memory Storage ....................................................................................... 39–4
Chain Assignment .................................................................................................................................... 39–4
Starting Chain Loading ............................................................................................................................ 39–4
Buffered Chain Loading Register.............................................................................................................. 39–4
TCB Storage............................................................................................................................................. 39–5
EMDMA Operating Modes......................................................................................................................... 39–7
Standard DMA ......................................................................................................................................... 39–8
Circular Buffered DMA............................................................................................................................ 39–8
Chained DMA Mode................................................................................................................................ 39–9
Data Direction On-the-Fly ..................................................................................................................... 39–10
Write Back Circular Index Pointer .......................................................................................................... 39–10
Scatter/Gather DMA .............................................................................................................................. 39–10
Pre Modified Read/Write Index .............................................................................................................. 39–12
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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