Analog Devices ADSP-SC58 Series Hardware Reference Manual page 775

Table 16-32: SPI_SLVSEL Register Fields (Continued)
Bit No.
(Access)
13 SSEL5
(R/W)
12 SSEL4
(R/W)
11 SSEL3
(R/W)
10 SSEL2
(R/W)
9 SSEL1
(R/W)
7 SSE7
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Slave Select 5 Output.
The SPI_SLVSEL.SSEL5 bit state indicates the value driven on the related
SPI_SEL[n] pin.
Slave Select 4 Output.
The SPI_SLVSEL.SSEL4 bit state indicates the value driven on the related
SPI_SEL[n] pin.
Slave Select 3 Output.
The SPI_SLVSEL.SSEL3 bit state indicates the value driven on the related
SPI_SEL[n] pin.
Slave Select 2 Output.
The SPI_SLVSEL.SSEL2 bit state indicates the value driven on the related
SPI_SEL[n] pin.
Slave Select 1 Output.
The SPI_SLVSEL.SSEL1 bit state indicates the value driven on the related
SPI_SEL[n] pin.
Slave Select 7 Enable.
The SPI_SLVSEL.SSE7 bit enables the related SPI_SEL[n] pin for output. If
disabled, the SPI three-states the related SPI_SEL[n] pin. When the SPI is a slave,
the master (not the SPI) asserts the input during the transfer. The input may be deas-
serted or remain asserted between transfers. While the input is deasserted, the SPI ig-
nores the SPI clock, ignores inputs, and three-states outputs.
ADSP-SC58x SPI Register Descriptions
Description/Enumeration
0 Low
1 High
0 Low
1 High
0 Low
1 High
0 Low
1 High
0 Low
1 High
0 Disable
1 Enable
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