Analog Devices ADSP-SC58 Series Hardware Reference Manual page 98

TRNG LFSR Access Register ................................................................................................................. 47–26
TRNG LFSR Access Register ................................................................................................................. 47–27
TRNG Monobit Test Result Register .................................................................................................... 47–28
TRNG Output Registers ....................................................................................................................... 47–29
TRNG Poker Test Result Registers ........................................................................................................ 47–30
TRNG Run Count Registers ................................................................................................................. 47–31
TRNG Run Test State and Result Registers ........................................................................................... 47–32
TRNG Status Register ........................................................................................................................... 47–34
TRNG Test Register .............................................................................................................................. 47–36
Thermal Monitoring Unit (TMU)
TMU Features ............................................................................................................................................. 48–1
TMU Functional Description ...................................................................................................................... 48–1
ADSP-SC58x TMU Register List............................................................................................................. 48–1
ADSP-SC58x TMU Interrupt List .......................................................................................................... 48–2
ADSP-SC58x TMU Trigger List .............................................................................................................. 48–2
TMU Definitions ..................................................................................................................................... 48–2
TMU Block Diagram ............................................................................................................................... 48–3
TMU Architectural Concepts ................................................................................................................... 48–3
TMU Event Control .................................................................................................................................... 48–4
Status and Error Signals............................................................................................................................ 48–4
TMU Programming Guidelines................................................................................................................... 48–5
ADSP-SC58x TMU Register Descriptions ................................................................................................. 48–5
Alert High Limit Register ........................................................................................................................ 48–6
Alert Low Limit Register ......................................................................................................................... 48–7
Averaging Register ................................................................................................................................... 48–8
TMU Control Register ............................................................................................................................ 48–9
Fault High Limit Register ...................................................................................................................... 48–10
Fault Low Limit Register ....................................................................................................................... 48–11
Gain Value Register ............................................................................................................................... 48–12
xcviii ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference