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TRU Functional Description
Table 8-4: ADSP-SC58x Trigger List Slaves (Continued)
Trigger ID
Name
71
STM0_EVT19
72
STM0_EVT20
73
STM0_EVT21
74
STM0_EVT22
75
STM0_EVT23
76
STM0_EVT24
77
STM0_EVT25
78
STM0_EVT26
79
STM0_EVT27
80
STM0_EVT28
81
STM0_EVT29
82
STM0_EVT30
83
STM0_EVT31
84
TRU0_SLV0
85
TRU0_SLV1
86
TRU0_SLV2
87
TRU0_SLV3
88
TRU0_SLV4
89
TRU0_SLV5
90
TRU0_SLV6
91
TRU0_SLV7
92
TRU0_SLV8
93
TRU0_SLV9
94
TRU0_SLV10
95
TRU0_SLV11
96
UART0_TXDMA
97
UART0_RXDMA
98
UART1_TXDMA
99
UART1_RXDMA
100
UART2_TXDMA
101
UART2_RXDMA
8–10
Description
STM0 Event 19
STM0 Event 20
STM0 Event 21
STM0 Event 22
STM0 Event 23
STM0 Event 24
STM0 Event 25
STM0 Event 26
STM0 Event 27
STM0 Event 28
STM0 Event 29
STM0 Event 30
STM0 Event 31
TRU0 Interrupt Request 0, core ID = 0 only
TRU0 Interrupt Request 1, core ID = 0 only
TRU0 Interrupt Request 2, core ID = 0 only
TRU0 Interrupt Request 3, core ID = 0 only
TRU0 Interrupt Request 4, core ID = 1 only
TRU0 Interrupt Request 5, core ID = 1 only
TRU0 Interrupt Request 6, core ID = 1 only
TRU0 Interrupt Request 7, core ID = 1 only
TRU0 Interrupt Request 8, core ID = 2 only
TRU0 Interrupt Request 9, core ID = 2 only
TRU0 Interrupt Request 10, Core ID = 2 only
TRU0 Interrupt Request 11, core ID = 2 only
UART0 Transmit DMA
UART0 Receive DMA
UART1 Transmit DMA
UART1 Receive DMA
UART2 Transmit DMA
UART2 Receive DMA
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Sensitivity
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
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