Cgu Pll Block Diagram - Analog Devices ADSP-SC58 Series Hardware Reference Manual

CGU Functional Description
CGU
The clock generation unit (CGU) is comprised of the PLL and PCU. The CGU generates the clocks listed in the
Clock Descriptions table.
Table 3-5: Clock Descriptions
Clock
CCLK0_0
CCLK1_0
SYSCLK_0
SCLK0_0
SCLK1_0
DCLK_0
OCLK_0
CCLK0_1
CCLK1_1
SYSCLK_1
SCLK0_1
SCLK1_1
DCLK_1
OCLK_1

CGU PLL Block Diagram

The CGU PLL Block Diagram provides a top-level block diagram of the phase locked loop (PLL). The main blocks
of the PLL are the phase/frequency detector (PFD), the charge pump, the loop filter, and the voltage controlled
oscillator (VCO). The VCO multiplies the SYS_CLKINx input to a higher frequency.
3–4
Description
CCLK0 derived from CGU0
CCLK1 derived from CGU0
SYSCLK derived from CGU0
SCLK0 derived from CGU0
SCLK1 derived from CGU0
DCLK derived from CGU0
OCLK derived from CGU0
CCLK0 derived from CGU1
CCLK1 derived from CGU1
SYSCLK derived from CGU1
SCLK0 derived from CGU1
SCLK1 derived from CGU1
DCLK derived from CGU1
OCLK derived from CGU1
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference