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Port x GPIO Input Enable Clear Register
The
PORT_INEN_CLR
PORT_INEN
register description.
PX15 (R/W1C)
Port x Bit 15 Input Enable Clear
PX14 (R/W1C)
Port x Bit 14 Input Enable Clear
PX13 (R/W1C)
Port x Bit 13 Input Enable Clear
PX12 (R/W1C)
Port x Bit 12 Input Enable Clear
PX11 (R/W1C)
Port x Bit 11 Input Enable Clear
PX10 (R/W1C)
Port x Bit 10 Input Enable Clear
PX9 (R/W1C)
Port x Bit 9 Input Enable Clear
PX8 (R/W1C)
Port x Bit 8 Input Enable Clear
Figure 14-18: PORT_INEN_CLR Register Diagram
Table 14-19: PORT_INEN_CLR Register Fields
Bit No.
(Access)
15
PX15
(R/W1C)
14
PX14
(R/W1C)
13
PX13
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register disables the input drivers for GPIO pins. For more information, see the
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Port x Bit 15 Input Enable Clear.
Port x Bit 14 Input Enable Clear.
Port x Bit 13 Input Enable Clear.
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 No Effect
1 Clear Bit. Set to disable the input driver.
0 No Effect
1 Clear Bit. Set to disable the input driver.
0 No Effect
1 Clear Bit. Set to disable the input driver.
ADSP-SC58x PORT Register Descriptions
1
0
0
0
PX0 (R/W1C)
Port x Bit 0 Input Enable Clear
PX1 (R/W1C)
Port x Bit 1 Input Enable Clear
PX2 (R/W1C)
Port x Bit 2 Input Enable Clear
PX3 (R/W1C)
Port x Bit 3 Input Enable Clear
PX4 (R/W1C)
Port x Bit 4 Input Enable Clear
PX5 (R/W1C)
Port x Bit 5 Input Enable Clear
PX6 (R/W1C)
Port x Bit 6 Input Enable Clear
PX7 (R/W1C)
Port x Bit 7 Input Enable Clear
17
16
0
0
14–51
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