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Status Register
The
register indicates status for modes selected with the
DMC_STAT
operations.
DLLCALDONE (R)
DLL Calibration Done
RESETDONE (R)
Reset Done
DPDACK (R)
Deep Power-Down Acknowledge
PDACK (R)
Power-Down Acknowledge
ZQCLDONE (R)
ZQ Calibration Long Done
ZQCSDONE (R)
ZQ Calibration Short Done
Figure 10-24: DMC_STAT Register Diagram
Table 10-33: DMC_STAT Register Fields
Bit No.
(Access)
25
ZQCLDONE
(R/NW)
24
ZQCSDONE
(R/NW)
23:20
PHYRDPHASE
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
Bit Name
ZQ Calibration Long Done.
The DMC_STAT.ZQCLDONE bit checks if the ZQ calibration long sub routine is
done.
ZQ Calibration Short Done.
The DMC_STAT.ZQCSDONE bit checks if the ZQ calibration short sub routine is
done.
PHY Read Phase.
The DMC_STAT.PHYRDPHASE bits indicate the latency after which the DMC may
read from the PHY. Taking round trip delay into account, the DLL indicates the exact
number of clock cycles after which the controller needs to read data. Values other than
those shown are reserved.
DMC_CTL
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
0 ZQ Calibration long is ongoing
1 ZQ Calibration long is done
0 ZQ Calibration short is ongoing
1 ZQ Calibration Short is done
ADSP-SC58x DMC Register Descriptions
register and indicates status DMC
1
0
0
1
IDLE (R)
Idle State
INITDONE (R)
Initialization Done
SRACK (R)
Self-Refresh Acknowledge
16
0
0
PENDREF (R)
Pending Refresh
PHYRDPHASE (R)
PHY Read Phase
10–61
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