Analog Devices ADSP-SC58 Series Hardware Reference Manual page 7

Message Set Bits Register ......................................................................................................................... 6–20
System Interface Disable Register ............................................................................................................ 6–21
System Interface Status Register .............................................................................................................. 6–22
Status Register ......................................................................................................................................... 6–23
Software Vector Register 0 ....................................................................................................................... 6–25
Software Vector Register 1 ....................................................................................................................... 6–26
Software Vector Register 2 ....................................................................................................................... 6–27
SVECT Lock Register .............................................................................................................................. 6–28
System Event Controller (SEC) and Generic Interrupt Controller (GIC)
SEC Features.................................................................................................................................................. 7–1
SEC Functional Description .......................................................................................................................... 7–2
ADSP-SC58x SEC Register List ................................................................................................................. 7–2
ADSP-SC58x SEC Interrupt List .............................................................................................................. 7–3
Combined SEC and GIC Interrupt List ..................................................................................................... 7–3
SEC Definitions ....................................................................................................................................... 7–12
SEC Block Diagram.................................................................................................................................. 7–13
SEC Fault Interface (SFI) ...................................................................................................................... 7–13
SEC Core Interface (SCI) ...................................................................................................................... 7–14
SEC Source Interface (SSI).................................................................................................................... 7–15
SEC Architectural Concepts ..................................................................................................................... 7–15
System Interrupt Acknowledge.............................................................................................................. 7–15
System Interrupt Groups....................................................................................................................... 7–16
System Interrupt Flow........................................................................................................................... 7–16
System Interrupt Priorities .................................................................................................................... 7–17
SEC Error.............................................................................................................................................. 7–17
SEC Programming Model............................................................................................................................ 7–17
Programming Concepts ............................................................................................................................ 7–18
Programming Examples............................................................................................................................ 7–18
Fault Management Interface Programming Model ................................................................................ 7–18
Configuring a System Source to Interrupt a Core.................................................................................. 7–19
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference vii