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memory-mapped access may be needed before setting the SPI_MMRDH.CMDSKIP bit in order to set the SPI
memory device in Command Skip mode.
For more details about how to configure SPI memories into XIP mode, refer to the device data sheet.
NOTE:
When configuring the flash to XIP mode from the SHARC+ core, ensure that the routine that configures
flash to XIP is not routed through the L2CC. This is accomplished by first configuring the flash to XIP
mode, then enabling the L2CC from the core.
Memory-Mapped Mode Error Status Bits
The SPI memory-mapped hardware provides bits in the
for notification only and their state has no effect on SPI operations. The status register bits are sticky. A W1C
(write-1-to-clear) operation clears the bits.
• Memory-Mapped Write Error (SPI_STAT.MMWE). This bit is set (=1) if an attempt is made to write to ad-
dress space that is reserved for memory-mapped SPI memory. The SPI memory-mapped hardware does not
support automated write access to SPI memory space.
• Memory-Mapped Read Error (SPI_STAT.MMRE). This bit is set (=1) if an attempt is made to read address
space reserved for memory-mapped SPI memory while memory mapping is disabled (SPI_CTL.MMSE =0).
• Memory-Mapped Access Error (SPI_STAT.MMAE). This bit is set (=1) if an attempt is made to access either
the TX or RX FIFO while memory-mapped access of SPI memory is enabled. In this case, attempts to commu-
nicate with the SPI device using legacy methods are blocked and receive fabric error responses. Legacy methods
include any direct access made to the TX and RX FIFOs, whether by DMA or processor MMR.
• Memory-Mapped Write Error Mask (SPI_CTL.MMWEM) bit specifies whether an error response is returned to
the fabric on write attempts to address space that is reserved for memory-mapped SPI memory reads. Regard-
less of whether a write error response is masked using this bit, the memory-mapped write error
(SPI_STAT.MMWE) sticky notification bit is still set.
NOTE:
Unlike other bits in the
sociated bits in the SPI interrupt mask (SPI_IMSK) and SPI interrupt condition (SPI_ILAT) reg-
isters.
The memory-mapped top register (SPI_MMTOP) is used to specify the upper limit of the SPI memory address. The
memory-mapped accesses to SPI memory addresses equal to or above this range are considered illegal. The accesses
are blocked and a bus error response is generated.
This register is useful to block the invalid SPI memory address accesses. Some SPI memory vendors do not clearly
specify (guarantee) that overrange address bits are ignored (address spaces can be wrapped).
Memory-Mapped Programming Guidelines
Seting the SPI_CTL.MMSE bit enables SPI memory-mapped mode. When enabled, the SPI interface is forced to
be consistent with SPI memory requirements regardless the settings of certain control bits. The following tables
specify typical settings for configuring the SPI in memory-mapped mode:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SPI_STAT
SPI_STAT
register, these memory-mapped mode error bits do not have as-
Memory-Mapped Mode (SPI2 only)
register to report errors. It provides these bits
16–25
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