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10 Dynamic Memory Controller (DMC)
The dynamic memory controller (DMC) provides a glueless interface between DDR3/DDR2/LPDDR SDRAMs
and the system crossbar interface (SCB). The DMC enables execution of instructions from, as well as transfer of
data to and from, DDR3, DDR2 SDRAM or LPDDR SDRAM respectively.
NOTE:
The terms DDR2, DDR3, and LPDDR SDRAM are referred to generically as DDR SDRAM in the rest
of this chapter unless otherwise noted.
According to JEDEC STD specification (JESD79‐3‐1A.01) DDR3L marked devices (1.35V) can also be
NOTE:
connected to ADSP-SC589 processors as these devices also meet 1.5V voltage level specifications of
DDR3 marked devices.
The DMC is partitioned in a manner that allows reconfiguration and maintainability. The memory access protocol
state machine along with JEDEC standard specific logic is embedded in the protocol controller. An access and opera-
tion reordering mechanism is incorporated as an efficiency controller. An SCB slave interface is provided to interface
with the on-chip interconnect. This interface results in an efficient slave implementation owing to its out-of-order
transaction capabilities. The control and status registers present in the DMC can be accessed using the MMR access
bus.
The DMC supports access to the external memory by core and DMA accesses.
DMC Features
The DMC includes a protocol controller that supports:
• JESD79-3E compatible double data rate DDR3 SDRAM devices
• JESD79-2E compatible DDR2 SDRAM devices
• JESD209A low-power DDR (LPDDR) SDRAM devices
The features of the dynamic memory controller are:
• Provides 16-bit data only interface to SDRAM devices
• Supports a single external rank (one chip select)
• Supports various burst lengths
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Dynamic Memory Controller (DMC)
10–1
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