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ECC Error Address 5 Register
The
L2CTL_ERRADDR5
The L2CTL updates this register only if the bank's status bit (L2CTL_STAT.ECCERR5) is cleared. After the
bank's status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit.
Figure 9-13: L2CTL_ERRADDR5 Register Diagram
Table 9-14: L2CTL_ERRADDR5 Register Fields
Bit No.
(Access)
31:0
VALUE
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register holds the address containing an ECC multi-bit error for the corresponding bank.
15
14
0
0
VALUE[15:0] (R)
ERRADDR Value
31
30
0
0
VALUE[31:16] (R)
ERRADDR Value
Bit Name
ERRADDR Value.
The L2CTL_ERRADDR5.VALUE bits hold the address containing the ECC double-
bit error.
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
1
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x L2CTL Register Descriptions
5
4
3
2
1
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
1
0
0
0
9–23
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