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ADSP-SC58x PADS Register Descriptions
DAI0 Port Input Enable Control Register
The
PADS_DAI0_IE
fer disable and if =1 implies enable.
VALUE[19:15] (R/W)
DAI0 Input Enable Control
Figure 14-35: PADS_DAI0_IE Register Diagram
Table 14-38: PADS_DAI0_IE Register Fields
Bit No.
(Access)
20:1
VALUE
(R/W)
14–104
register configures input enable control of the DAI0 (20 pins) pads. If =0 implies input buf-
15
0
VALUE[14:0] (R/W)
DAI0 Input Enable Control
31
0
Bit Name
DAI0 Input Enable Control.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
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