Analog Devices ADSP-SC58 Series Hardware Reference Manual page 579

Pairs of bits in the PORT_MUX
individual pin, as some PORT pins provide up to four possible peripheral functions.
Refer to the Signal Muxing table in the datasheet for the specific
PORT Event Control
The following sections describe event generation in the PORT module.
PORT Interrupt Signals
The pin interrupts are decoupled from GPIO functionality, providing the following advantages.
• Flexible mapping scheme enables pins from up to four different ports to be grouped into one common inter-
rupt scheme.
• Interrupt requests work on input and output pins regardless of whether the pin is functioning as a GPIO or a
peripheral.
The processor has a number of interrupt channels dedicated to pin interrupts, managed by a set of pin interrupt
(PINTx) blocks. Each PINTx block can sense up to 32 GPIO pins, as described in the following list and figure.
• PINT0 can sense pin activity on PORTA and PORTB
• PINT1 can sense pin activity on PORTB and PORTC
• PINT2 can sense pin activity on PORTC and PORTD
• PINT3 can sense pin activity on PORTD and PORTE
• PINT4 can sense pin activity on PORTE and PORTF
• PINT5 can sense pin activity on PORTF and PORTG. Note that PORTF and PORTG are not available on
the low pin count package.
The processor supports both 32-bit and 16-bit peripheral bus accesses to PINTx registers.
Figure 14-2: GPIO to PINTx Assignment
Pins connect to the PINTx module and then to the system event controller (SEC), as shown in the PINTx Block
Diagram.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register control the multiplexing between the peripheral functions available to an
IRQ16 IRQ17 IRQ18
PINT0 PINT1 PINT2
PORTA PORTB PORTC
PORT_MUX settings.
IRQ19 IRQ20 IRQ21
PINT3 PINT4 PINT5
PORTD PORTE PORTF*
*PORTF and PORTG are not available
on the 349-ball BGA package
(see the product specific data sheet).
PORT Event Control
PORTG*
14–7