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ADSP-SC58x UART Register Descriptions
Receive Buffer Register
The read-only
UART_RBR
receive FIFO. Newly available data is signaled by the UART_STAT.DR bit.
Figure 17-16: UART_RBR Register Diagram
Table 17-15: UART_RBR Register Fields
Bit No.
(Access)
7:0
VALUE
(R/NW)
17–40
register is the UART's receive buffer. It is updated when there is pending data in the
15
14
13
12
0
0
0
VALUE (R)
8-bit data
31
30
29
28
0
0
0
Bit Name
8-bit data.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
Description/Enumeration
4
3
2
1
0
0
0
0
0
0
19
18
17
16
0
0
0
0
0
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