Analog Devices ADSP-SC58 Series Hardware Reference Manual page 37

Sharc+ processor
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ACM External Pin Timing ....................................................................................................................... 24–6
ACM Architectural Concepts.................................................................................................................. 24–10
Clocking.............................................................................................................................................. 24–10
Block Diagram .................................................................................................................................... 24–10
Trigger Inputs ..................................................................................................................................... 24–11
Timers................................................................................................................................................. 24–13
Event Register Pairs............................................................................................................................. 24–14
Event Comparators Unit ..................................................................................................................... 24–14
Timing Generation Unit ..................................................................................................................... 24–15
Status Flags and Interrupts .................................................................................................................. 24–15
Event Order Registers.......................................................................................................................... 24–16
ACM Operation ........................................................................................................................................ 24–17
ACM Programming Concepts ................................................................................................................... 24–18
Emulation Mode Use Case...................................................................................................................... 24–20
ADSP-SC58x ACM Register Descriptions ................................................................................................ 24–22
Control Register .................................................................................................................................... 24–23
Event N Control Register ...................................................................................................................... 24–26
Event Complete Interrupt Mask Register ............................................................................................... 24–27
Event N Order Register ......................................................................................................................... 24–30
Event Complete Status Register ............................................................................................................. 24–31
Event N Time Register .......................................................................................................................... 24–36
Missed Event Interrupt Mask Register ................................................................................................... 24–37
Missed Event Status Register ................................................................................................................. 24–40
Status Register ....................................................................................................................................... 24–44
Timing Configuration 0 Register ........................................................................................................... 24–46
Timing Configuration 1 Register ........................................................................................................... 24–47
Timer 0 Register .................................................................................................................................... 24–48
Timer 1 Register .................................................................................................................................... 24–49
Controller Area Network (CAN)
CAN Features .............................................................................................................................................. 25–1
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
xxxvii

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