Table of Contents
Advertisement
L2 Memory Controller (L2CTL)
L2 System Memory
has significant bandwidth for core accesses, but it is important to note that L2 responds slower
to core accesses than L1 memories. L2 SRAM is the ideal storage for multiple processor cores to share data and
instruction resources, such as semaphores, shared buffers, and code libraries. Due to sophisticated data integrity pro-
tection and write protection, L2 SRAM is also ideal for data and instructions critical for safe operation of the appli-
cation.
System MMR Write-Protection (WP115-117) from SPU
Enable Secure Peripheral (SECUREP115-117) from SPU
Figure 1-7: L2CTL System Diagram
Dynamic Memory Controller (DMC)
The
Dynamic Memory Controller (DMC)
and the system crossbar interface (SCB). The DMC enables execution of instructions from, as well as transfer of
data to and from, DDR3, DDR2 SDRAM or LPDDR SDRAM, respectively.
The DMC is partitioned in a manner that allows reconfiguration and maintainability. The memory access protocol
state machine along with JEDEC standard specific logic is embedded in the protocol controller. An access and oper-
ation reordering mechanism is incorporated as an efficiency controller. An SCB slave interface is provided to inter-
face with the on-chip interconnect. This interface results in an efficient slave implementation owing to its out-of-
order transaction capabilities.
The DMC supports access to the external memory by core and DMA accesses.
System MMR Write-Protection (WP109-114) from SPU
Enable Secure Peripheral (SECUREP109-114) from SPU
Figure 1-8: DMC System Diagram
Static Memory Controller (SMC)
The
Static Memory Controller (SMC)
cessor bus and the external L3 memory. It provides a glueless interface to various external memories and peripheral
devices, including SRAM, ROM, EPROM, NOR flash memory and FPGA/ASIC devices.
The SMC acts as an SCB slave. The processor SCB interconnect fabric arbitrates accesses to the SMC. The SMC
connects to signal pins for memory control (such as read, write, output enable, and memory select lines).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
System MMR Write-Protection from SMPU2-7
Clocked by SYSCLK_0 from CGU0
provides a glueless interface between DDR3/DDR2/LPDDR SDRAMs
System Memory Protection from SMPU9-10
Clocked by DCLK_x (Selected in CDU)
is a protocol converter and data transfer interface between the internal pro-
System Memory (L2CTL/DMC/SMC/OTPC/SMPU)
L2CTL
L2 ECC Error Event (L2CTL0_ECC_ERR) to SEC/GIC
Core/Cache Access Arbitration in SCB0 Only
DMA Access Arbitration Among Numerous SCBs
DMC
DDR Address Pins (DMCx_A15:00)
DDR Data Pins (DMCx_DQ15:00)
∙ Core/Cache Access Arbitration in SCB0 Only
∙ DMA Access Arbitration Among Numerous SCBs
DDR Clock Pin (DMCx_CK)
DDR Control Reference Pins
∙ All DMCx_ Pins Not Detailed Above
1–5
Advertisement
Table of Contents
