Table of Contents
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Features........................................................................................................................................................ 52–1
Clocking ...................................................................................................................................................... 52–1
Functional Description ................................................................................................................................ 52–1
ADSP-SC58x IIR Register List................................................................................................................. 52–3
ADSP-SC58x IIR Interrupt List .............................................................................................................. 52–4
ADSP-SC58x IIR Trigger List .................................................................................................................. 52–4
Multiply and Accumulate (MAC) Unit ..................................................................................................... 52–4
Input Data and Biquad State .................................................................................................................... 52–5
Coefficient Memory ................................................................................................................................. 52–5
Internal Memory Storage.......................................................................................................................... 52–5
Coefficient Memory Storage.................................................................................................................. 52–5
Operating Modes ......................................................................................................................................... 52–6
Window Processing Mode ........................................................................................................................ 52–6
40-Bit Floating-Point Mode ..................................................................................................................... 52–6
Save Biquad State Mode ........................................................................................................................... 52–6
Data Transfers.............................................................................................................................................. 52–7
IIR Accelerator TCB................................................................................................................................. 52–7
DMA Access.......................................................................................................................................... 52–8
Chain Pointer DMA .......................................................................................................................... 52–8
Effect Latency........................................................................................................................................... 52–9
Write Effect Latency .............................................................................................................................. 52–9
IIR Throughput ....................................................................................................................................... 52–9
Interrupts................................................................................................................................................... 52–10
Sources .................................................................................................................................................. 52–10
Window Complete .............................................................................................................................. 52–10
All Channels Complete ....................................................................................................................... 52–10
Chained DMA ................................................................................................................................... 52–10
MAC Status ........................................................................................................................................ 52–10
Service .................................................................................................................................................... 52–11
Programming Model.................................................................................................................................. 52–11
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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Table of Contents
