Analog Devices ADSP-SC58 Series Hardware Reference Manual page 748

ADSP-SC58x SPI Register Descriptions
Table 16-19: SPI_CTL Register Fields (Continued)
Bit No.
(Access)
3 ODM
(R/W)
2 PSSE
(R/W)
1 MSTR
(R/W)
0 EN
(R/W)
16–42
Bit Name
Open Drain Mode.
The SPI_CTL.ODM bit configures the data output pins (SPI_MOSI and
SPI_MISO) to behave as open drain outputs, which prevents contention and possible
damage to pin drivers in multi-master or multi-slave SPI systems.
When SPI_CTL.ODM is enabled and the SPI is a master, the SPI three-states the
SPI_MOSI pin when the data driven out on MOSI is a logic-high. The SPI does not
three-state the SPI_MOSI pin when the driven data is a logic-low.
When SPI_CTL.ODM is enabled and the SPI is a slave, the SPI three-states the
SPI_MISO pin when the data driven out on SPI_MISO is a logic-high.
Note that an external pull-up resistor is required on both the SPI_MOSI and
SPI_MISO pins when SPI_CTL.ODM is enabled.
Protected Slave Select Enable.
The SPI_CTL.PSSE bit enables the SPI_SS pin to provide error detection input
in a multi-master environment when the SPI is in master mode. If some other device
in the system asserts the SPI_SS pin while SPI is enabled as master (and
SPI_CTL.PSSE is enabled), this condition causes a mode fault error.
Master/Slave.
The SPI_CTL.MSTR bit toggles the SPI between master mode and slave mode. This
bit can only be changed when the SPI is disabled.
Enable.
The SPI_CTL.EN bit enables SPI operation.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Disable
1 Enable
0 Disable
1 Enable
0 Slave
1 Master
0 Disable SPI module
1 Enable