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ADSP-SC58x PWM Register Descriptions
Channel A-High Heightened-Precision Duty-1 Register
The
register provides a fine-grained edge placement within the system clock period. This register, in
PWM_AH1_HP
conjunction with the
PWM_AH0
ter and the
PWM_AH1
register work together in a Q15.8 signed two's complement fixed-point format.
Note that the bit fields in the
register (if available).
Figure 19-32: PWM_AH1_HP Register Diagram
Table 19-10: PWM_AH1_HP Register Fields
Bit No.
(Access)
7:6
ENHDIV
(R/W)
19–48
register, allows programs to specify fractional duty cycles.The
and the
PWM_AH1_HP
15
14
13
0
0
0
ENHDIV (R/W)
Enhanced Precision Divider Bits
31
30
29
0
0
0
Bit Name
Enhanced Precision Divider Bits.
The PWM_AH1_HP.ENHDIV bits provide fractional duty cycles for Channel A high
side output.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers are also present in the single full duty
PWM_AH1
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
PWM_AH1_HP
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
regis-
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