Analog Devices ADSP-SC58 Series Hardware Reference Manual page 746

ADSP-SC58x SPI Register Descriptions
Table 16-19: SPI_CTL Register Fields (Continued)
Bit No.
(Access)
14 FCCH
(R/W)
13 FCEN
(R/W)
12 LSBF
(R/W)
10:9 SIZE
(R/W)
8 EMISO
(R/W)
16–40
Bit Name
Flow Control Channel Selection.
The SPI_CTL.FCCH bit selects whether the SPI applies flow control to the transmit
channel
applicable only when the SPI is a slave and flow control is enabled.
Flow Control Enable.
The SPI_CTL.FCEN bit enables SPI flow control operation, which permits slow
slave devices to interface with fast master devices. This bit controls the operation of the
SPI_RDY pin.
Note that options for flow control operation are available using the SPI_CTL.FCCH,
SPI_CTL.FCPL, and SPI_CTL.FCWM bits.
Least Significant Bit First.
The SPI_CTL.LSBF bit selects whether the SPI transmits/receives data as LSB first
(little endian) or MSB first (big endian). This bit can only be changed when the SPI is
disabled.
Word Transfer Size.
The SPI_CTL.SIZE bits select the SPI transfer word size as 8, 16 or 32 bits. To
ensure correct operation, both the master and slave must be configured with the same
word size. This bit can only be changed when the SPI is disabled (SPI_CTL.EN =0).
Enable MISO.
The SPI_CTL.EMISO bit enables master-in-slave-out (MISO) mode. This SPI
mode is applicable only when the SPI is a slave.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
(SPI_TFIFO buffer) or receive channel
0 Flow control on RX buffer
1 Flow control on TX buffer
0 Disable
1 Enable
0 MSB sent/received first (big endian)
1 LSB sent/received first (little endian)
0 8-bit word
1 16-bit word
2 32-bit word
3 Reserved
0 Disable
1 Enable
(SPI_RFIFO buffer). This bit is