Analog Devices ADSP-SC58 Series Hardware Reference Manual page 726

Sharc+ processor
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Memory-Mapped Mode (SPI2 only)
Table 16-8: SPI Read Operations (Continued)
Operation
Read Command
(Opcode)
Quad I/O Read
0xEB
Some memory devices also support word quad I/O read (0xE7) and octal quad I/O read (0xE3) operations. These
operations require fewer dummy cycles than normal quad I/O read operations.
SSEL
SCK
MOSI
MISO
M = 1, 2, 3, 4 ADDRESS BYTES
N = 4, 8, 16, 32 READ DATA BYTES
Z = 0, 8, 16, 24, ..., 56 BUS TURN AROUND CYCLES
* = 1 DATA BIT iS SENT PER CLOCK PERIOD ON MISO
Figure 16-15: SPI Flash Fast Read Sequence
SSEL
SCK
MOSI
(Q0)
MISO
(Q1)
M = 1, 2, 3, 4 ADDRESS BYTES
N = 4, 8, 16, 32 READ DATA BYTES
Z = 0, 4, 12, ..., 28 BUS TURN AROUND CYCLES
* = 2 DATA BITS ARE SENT PER CLOCK PERIOD ON Q<1:0>
Figure 16-16: SPI Flash Fast Read (Dual Output) Sequence
16–20
CMDPIN
ADRPIN
1, 4
4
READ CMD
ADDRESS
1 BYTE
M BYTES
READ CMD
ADDRESS
1 BYTE
M BYTES
ADDRESS
M BYTES
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMYSIZE Three-state Multiple
Non-Zero
Yes
CONTINUOUS
CLOCKING
Z
MODE
HI-Z
BITS
CONTINUOUS
CLOCKING
Z
HI-Z
MODE
BITS
HI-Z
MODE
BITS
Data Pins
I/O Mode
Yes (IO0-3) 4
READ DATA
N BYTES (*)
N x 4 CLOCKS
READ DATA
N BYTES (*)
READ DATA
N BYTES (*)

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