Table of Contents
Advertisement
Status Interrupts
The SPI controller supports several status interrupt requests to indicate different conditions of the receiver and
transmitter. All status interrupt requests can be masked. Status interrupt requests are signaled directly through a sin-
gle SPI status IRQ line. The line cannot be combined with the SPI error IRQ line for some processors. The SPI
Status Interrupts table describes the status interrupt requests that are available for the SPI controller.
Table 16-15: SPI Status Interrupts
SPI_STAT Bit
SPI_STAT.RUWM
SPI_STAT.TUWM
SPI_STAT.TS
SPI_STAT.RS
SPI_STAT.TF
SPI_STAT.RF
Error Conditions
The SPI controller supports interrupt requests upon several different error conditions. All interrupt requests are
maskable. The individual error indications combine into a single SPI error IRQ signal, which can be multiplexed on
some processors with the aggregated SPI status IRQ signal. The SPI Error Interrupts table details the possible error
indications.
Error conditions arise depending on which of the channels (transmit or receive) are enabled. If a channel is disabled,
all errors related to it are ignored. When both channels are enabled, errors from both channels are enabled.
Table 16-16: SPI Error Interrupts
Bit
SPI_STAT.MF
SPI_STAT.TUR
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Receive FIFO urgent watermark interrupt request. Issued when the level of the RFIFO breaches the water-
mark set in the SPI_RXCTL.RUWM field. It is cleared when the level of the RFIFO reaches the watermark
set in the SPI_RXCTL.RRWM field. If the RX channel is configured in DMA mode, SPI_RXCTL.RUWM
is multiplexed with the data request.
Receive FIFO urgent watermark interrupt request. Issued when the level of the TFIFO breaches the water-
mark set using the SPI_TXCTL.TUWM bit. It is cleared when the level of the TFIFO reaches the watermark
set in the SPI_TXCTL.TRWM field. If the TX channel is configured in DMA mode, SPI_STAT.TUWM is
multiplexed with the data request.
Transmit start interrupt request. Issued when the start of a transmit burst is detected by loading of the
register with the contents of the
SPI_TWC
Receive start interrupt request. Issued when the start of a receive burst is detected by the loading of
SPI_RWC
with the contents of SPI_RWCR.
Transmit finish interrupt request. Issued when a transmit burst completes
Receive finish interrupt request. Issued when a receive burst completes
Description
Mode fault. Signaled when another device also tries to be a master in a multi-master system and drives the
SPI_SS input low. This error is signaled in master mode operation.
Transmission error. Signaled when an underflow condition occurs on the transmit channel. This event occurs
when a new transfer starts but
mode since
Not Empty is one of the conditions for transfer initiation.
SPI_TFIFO
register.
SPI_TWCR
is empty. This error does not occur in master transmit initiating
SPI_TFIFO
SPI Interrupt Signals
(SPI_TWC
decrements to zero).
(SPI_RWC
decrements to zero).
16–29
Advertisement
Table of Contents
