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Control Register
The
register enables the SPI and configures settings for operating modes, communication protocols, and
SPI_CTL
buffer operations.
FCPL (R/W)
Flow Control Polarity
FCCH (R/W)
Flow Control Channel Selection
FCEN (R/W)
Flow Control Enable
LSBF (R/W)
Least Significant Bit First
SIZE (R/W)
Word Transfer Size
EMISO (R/W)
Enable MISO
SELST (R/W)
Slave Select Polarity Between Transfers
MMSE (R/W)
Memory-Mapped SPI Enable (Only on
SPI2)
MMWEM (R/W)
Memory Mapped Write Error Mask (Only
on SPI2)
SOSI (R/W)
Start on MOSI (Only on SPI2)
Figure 16-21: SPI_CTL Register Diagram
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
ADSP-SC58x SPI Register Descriptions
EN (R/W)
Enable
MSTR (R/W)
Master/Slave
PSSE (R/W)
Protected Slave Select Enable
ODM (R/W)
Open Drain Mode
CPHA (R/W)
Clock Phase
CPOL (R/W)
Clock Polarity
ASSEL (R/W)
Slave Select Pin Control
FCWM (R/W)
Flow Control Watermark
FMODE (R/W)
Fast-Mode Enable
MIOM (R/W)
Multiple I/O Mode (Only on SPI2)
16–37
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