Analog Devices ADSP-SC58 Series Hardware Reference Manual page 27

Configuring 16-Bit Receive Mode ....................................................................................................... 18–37
Configuring 18-Bit Receive Mode ....................................................................................................... 18–38
Configuring 8-Bit Split Receive Mode................................................................................................. 18–39
Configuring 10/12/14/16-Bit Split Receive Mode with SPLTWRD=0 ............................................... 18–42
Configuring 16-Bit Split Receive Mode with SPLTWRD=1................................................................ 18–43
Configuring 8-Bit Transmit Mode....................................................................................................... 18–44
Configuring 10/12/14-Bit Transmit Modes ........................................................................................ 18–45
Configuring 16-Bit Transmit Mode..................................................................................................... 18–45
Configuring 18-Bit Transmit Mode..................................................................................................... 18–46
Configuring 8-Bit Split Transmit Mode .............................................................................................. 18–46
Configuring 10/12/14/16-Bit Transmit Mode with SPLTWRD=0 ..................................................... 18–49
Configuring 16-Bit Split Transmit Mode with SPLTWRD=1 ............................................................. 18–51
EPPI Programming Concepts................................................................................................................. 18–52
ADSP-SC58x EPPI Register Descriptions ................................................................................................ 18–52
Clock Divide Register ............................................................................................................................ 18–54
Control Register .................................................................................................................................... 18–55
Control Register 2 Register .................................................................................................................... 18–63
Clipping Register for EVEN (Luma) Data Register ............................................................................... 18–64
Lines Per Frame Register ....................................................................................................................... 18–65
Frame Sync 1 Delay Value Register ........................................................................................................ 18–66
FS1 Period Register / EPPI Active Samples Per Line Register ................................................................ 18–67
FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register ......................................... 18–68
Frame Sync 2 Delay Value Register ........................................................................................................ 18–69
FS2 Period Register / EPPI Active Lines Per Field Register .................................................................... 18–70
FS2 Width Register / EPPI Lines Of Vertical Blanking Register ............................................................ 18–71
Horizontal Transfer Count Register ....................................................................................................... 18–72
Horizontal Delay Count Register .......................................................................................................... 18–73
Interrupt Mask Register ......................................................................................................................... 18–74
Samples Per Line Register ...................................................................................................................... 18–76
Clipping Register for ODD (Chroma) Data Register ............................................................................ 18–77
Status Register ....................................................................................................................................... 18–78
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference xxvii