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Feature Exclusions
The DMC exclusions are as follows:
For DDR2:
• 4-bit and 8-bit wide DDR2 DRAM memories are not supported
• OCD is not supported
• Burst interleaved accesses are not supported
• Single-ended signaling mode not supported
For DDR3:
• 4-bit and 8-bit wide DDR2 DRAM memories are not supported
• Burst interleaved accesses are not supported
• Both burst chop-BC4 and BC4-on-the-fly are not supported
• Auto refresh pull-in is not supported
• Write leveling is not supported
• DLL off mode is not supported
For LPDDR:
• 32-bit wide LPDDR memory devices are not supported
• Status register read (SRR) is not supported
• Sampling the optional temperature output (TQ) signal is not supported
• Clock stop mode is not supported
• Bursts of 2 and 16 words are not supported
• No support for BURST_TERMINATE command
• Dual-die, two CS# and two CKE packages are not supported
DMC Functional Description
The dynamic memory controller consists of master and slave interfaces, a protocol controller, and an efficiency con-
troller. The following sections describe the function of these interfaces and controllers.
ADSP-SC58x DMC Register List
The Dynamic Memory Controller module (DMC) provides an interface to external double-data-rate SDRAM. This
interface supports various DDR standards (see chapter descriptions). A set of registers governs DMC controller op-
erations. For more information on DMC controller functionality, see the DMC Controller Register Descriptions.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMC Features
10–3
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