Table of Contents
Advertisement
ADSP-SC58x UART Register Descriptions
Status Register
The
register contains the UART line status and UART modem status, as indicated by the current
UART_STAT
states of the UART's UART_CTS pin and internal receive buffers. Writes to this register can perform write-one-to-
clear (W1C) operations on most status bits. Reading this register has no side effects.
SCTS (R/W1C)
Sticky CTS
RO (R)
Reception On-going
ADDR (R/W1S)
Address Bit Status
ASTKY (R/W1C)
Address Sticky
TFI (R/W1C)
Transmission Finished Indicator
TEMT (R)
TSR and THR Empty
RFCS (R)
Receive FIFO Count Status
Figure 17-20: UART_STAT Register Diagram
Table 17-19: UART_STAT Register Fields
Bit No.
(Access)
17
RFCS
(R/NW)
17–44
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
Bit Name
Receive FIFO Count Status.
The UART_STAT.RFCS bit is set when the receive buffer holds more or equal entries
than a certain threshold. The threshold is controlled by the UART_CTL.RFIT bit. If
UART_CTL.RFIT is cleared, the threshold is four entries. If UART_CTL.RFIT is
set, the threshold is seven entries. The UART_STAT.RFCS bit is cleared when the
UART_RBR
threshold. The UART_STAT.RFCS bit can trigger a status interrupt request if ena-
bled by the UART_IMSK_SET.ERFCI bit.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
8
7
6
5
4
3
2
1
0
1
0
1
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
register is read sufficient times until the buffer is drained below the
0 RX FIFO has less than 4 (7) entries when RFIT=0 (1)
1 RX FIFO has at least 4 (7) entries when RFIT=0 (1)
0
0
DR (R)
Data Ready
OE (R/W1C)
Overrun Error
PE (R/W1C)
Parity Error
FE (R/W1C)
Framing Error
BI (R/W1C)
Break Indicator
THRE (R)
Transmit Hold Register Empty
0
CTS (R)
Clear to Send
Advertisement
Table of Contents
