Table of Contents
Advertisement
Port x GPIO Lock Register
The
register enables (unlocks) or disables (locks) write access selectively for the PORT control regis-
PORT_LOCK
ters.
POLAR (R/W)
Polarity Lock
INEN (R/W)
Input Enable Lock
DIR (R/W)
Direction Lock
LOCK (R/W)
Lock
Figure 14-20: PORT_LOCK Register Diagram
Table 14-21: PORT_LOCK Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
5
POLAR
(R/W)
4
INEN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
0
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
0
Bit Name
Lock.
If the global lock bit is set (SPU_CTL.GLCK bit =1) and the PORT_LOCK.LOCK
bit is set, the
Polarity Lock.
The PORT_LOCK.POLAR disables write access to the PORT_POL,
PORT_POL_SET, and
Input Enable Lock.
The PORT_LOCK.INEN disables write access to the PORT_INEN,
PORT_INEN_SET, and
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
Description/Enumeration
PORT_LOCK
register is read only (locked).
0 Unlock
1 Lock
PORT_POL_CLR
0 Unlock POL
1 Lock POL
PORT_INEN_CLR
0 Unlock INEN
1 Lock INEN
ADSP-SC58x PORT Register Descriptions
0
0
FER (R/W)
Function Enable Lock
MUX (R/W)
Function Multiplexer Lock
DATA (R/W)
Data, TGL Lock
16
0
registers.
registers.
14–57
Advertisement
Table of Contents
