Analog Devices ADSP-SC58 Series Hardware Reference Manual page 186

Table 3-19: CGU_STAT Register Fields (Continued)
Bit No.
(Access)
3 CLKSALGN
(R/NW)
2 PLOCK
(R/NW)
1 PLLBP
(R/NW)
0 PLLEN
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Clock Alignment.
The CGU_STAT.CLKSALGN bit indicates whether a clock alignment sequence is in
progress. This bit is set when clocks alignment is required by changes to
CGU_DIV.CSEL, CGU_DIV.S0SEL, CGU_DIV.S1SEL, CGU_DIV.DSEL, or
CGU_DIV.OSEL. The CGU_STAT.CLKSALGN bit is cleared when clocks are
aligned.
Note that (after a PLL frequency change in active state) the CGU_STAT.CLKSALGN
bit may indicate that clocks are not aligned even though the clocks are aligned (all
clocks are aligned and running at CLKIN frequency).
PLL Lock.
The CGU_STAT.PLOCK bit indicates whether the PLL is locked. This bit is set when
the PLL locks (PLL lock counter end-of-count). The CGU_STAT.PLOCK bit is
cleared when requested PLL frequency change (for PLL reset, PLL disable-to-enable
transition, or a change to the CGU_CTL.MSEL or CGU_CTL.DF values) is in prog-
ress.
PLL Bypass.
The CGU_STAT.PLLBP bit indicates whether the PLL is bypassed. The default val-
ue for the CGU_STAT.PLLBP bit is determined by the bypass strap pin.
PLL Enable.
The CGU_STAT.PLLEN bit indicates whether the PLL is enabled.
ADSP-SC58x CGU Register Descriptions
Description/Enumeration
2 Subharmonic CLKIN
3 Harmonic CLKIN
4 No AUX_CLK
5 CLKIN > Upper Frequency Limit (BOUF)
6 Reserved
7 Multiple Limit Faults
0 Clocks are Aligned
1 Clocks not Aligned (alignment in progress)
0 PLL not Locked (PLL frequency change in progress)
1 PLL Locked
0 PLL not Bypassed
1 PLL Bypassed
0 Disabled
1 Enabled
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