Analog Devices ADSP-SC58 Series Hardware Reference Manual page 851

EPPI Architectural Concepts
• Setting
DMA_XCNT
half of the frame is transferred, and again when the whole frame is transferred.
The following is the general procedure for setting up DMA operation with the EPPI.
1. Configure the DMA registers as appropriate for the desired DMA operating mode.
2. Enable the DMA channel for operation.
3. Configure appropriate EPPI registers.
4. Enable the EPPI by writing 1 to the EPPI_CTL.EN bit.
EPPI Clock
The EPPI can be supplied with an external clock, or the clock can be generated internally and supplied to external
devices. For information on the maximum PPI_CLK specification in internal and external clock modes, see the
product-specific data sheet.
When using an external EPPI_CLK, there can be up to two cycles latency before valid data is received or transmit-
ted.
The internal clock can be generated from SCLK1_0 when the EPPI_CTL.ICLKGEN bit is set. The value in the
EPPI_CLKDIV register determines the generated clock frequency. The internally generated EPPI clock frequency
is:
f = f /(EPPI_CLKDIV
PCLK SCLK0
where:
f – frequency of internally generated EPPI clock
PCLK
f – frequency of SCLK1_0
SCLK
EPPI_CLKDIV – Clock division value programmed in the
The Relationship Between CLKDIV and the Ratio of SCLK0 to EPPI Clock table gives a few examples.
Table 18-8: Relationship Between CLKDIV and the Ratio of SCLK0 to EPPI Clock
CLKDIV15–0
0x0002
0x0003
0x0004
0x0005
...
18–12
=38,400 (320 x 120), DMA_YCNT
+ 1)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
=2, and DMA_CFG.INT =1 causes an interrupt when
EPPI_CLKDIV register.
EPPI/SCLK0 Clock Ratio
1:3
1:4
1:5
1:6
...