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Register Access Features
For more information regarding the sequencer registers, see "Program
Sequencer" in the ADSP-TS101 TigerSHARC Processor Programming
Reference.
Sequencer Control Register – SQCTL
The sequencer is controlled and configured by writing to the
ter, which is set to 0x0100 after reset.
Sequencer Control Register Set Bits – SQCTLST
The
bit is an alias used to write to
SQCTLST
address, the data written into
the new data written into
the corresponding bit in
the bit value.
Sequencer Control Register Clear Bits – SQCTLCL
The
bit is an alias used to write to
SQCTLCL
address, the data written into
and the new data written into
written data clears the corresponding bit in
data does not change the bit value.
Sequencer Status Register – SQSTAT
This is a read-only register that holds information about the current status
of the sequencer. The initial value of this register after reset is 0xFF00.
SFREG Register
Static flags are used as static copies of conditions. When the programmer
wishes to keep a condition value after another instruction changes its
value, it can be copied into the
2-16
is the OR of the old register value and
SQCTL
. A '1' in any bit of the written data sets
SQCTLST
, while a '0' in written data does not change
SQCTL
is the AND of the old register value
SQCTL
. This way a '0' in any bit of the
SQCTLCL
and used later as a condition. All
SFREG
ADSP-TS101 TigerSHARC Processor
When writing to this
SQCTL.
. When writing to this
SQCTL
, while a '1' in written
SQCTL
Hardware Reference
regis-
SQCTL
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