Arm Cortex-A5 Sub-System; Cortex A5 Features - Analog Devices ADSP-SC58 Series Hardware Reference Manual

2 ARM Cortex-A5 Sub-System

The ADSP-SC589 processor includes an ARM
lowest cost and lowest power ARMv7 application processor. The A5 sub-system in the ADSP-SC589 processor in-
cludes a Floating-Point Unit, NEON Media Processing Engine, Generic Interrupt Controller and a Level 2 Cache
Controller. The A5 also includes support for a L1-Cache sub-system and a full-fledged Memory Management Unit.
The A5 implements the ARMv7 architecture and runs 32-bit ARM instructions, 16-bit and 32-bit Thumb instruc-
tions, and 8-bit Java byte-codes in Jazelle state.
This document describes the ARM Cortex-A5 core and memory architecture used on the ADSP-SC58x processor,
but does not provide detailed programming information for the ARM processor. For more information about pro-
gramming the ARM processor, visit the ARM Information Center:
• http://infocenter.arm.com.
The applicable documentation for programming the ARM Cortex-A5 processor include:
• Cortex-A5 Technical Reference Manual, Revision: r0p1
• Cortex-A Series Programmer's Guide, Revision: r0p1
• Cortex-A5 NEON Media Processing Engine Technical Reference Manual, Revision: r0p1
• Cortex-A5 Floating-Point Unit Technical Reference Manual, Revision: r0p1
• CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual, Revision: r3p3
• PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual, Revision: r0p0

Cortex A5 Features

The Cortex-A5 Sub-system has the following features.
• Thumb / ARM Instruction support
• L1- Instruction Cache and L1-Data Cache
• Floating Point Unit (FPU)
• NEON Media Processing Engine (NEON)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
® ®
Cortex-A5 core. The ARM Cortex-A5 processor is the smallest,
ARM Cortex-A5 Sub-System
2–1