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SCI Control Register n
The SEC control register (SEC_CCTL[n]) contains SCI control bits for all system sources.
WFI (R0/W)
Wait For Idle
RESET (R0/W)
Reset
LOCK (R/W)
Lock
Figure 7-7: SEC_CCTL[n] Register Diagram
Table 7-6: SEC_CCTL[n] Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
16
NMIEN
(R/W)
12
WFI
(R0/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
Bit Name
Lock.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the
SEC_CCTL[n].LOCK bit is enabled, the
NMI Enable.
The SEC_CCTL[n].NMIEN bit controls NMI propagation to the core. When the
SEC_CCTL[n].NMIEN bit is enabled, the SCI allows NMIs to propagate to the
core for servicing.
Wait For Idle.
When set, the SEC_CCTL[n].WFI bit forces the SCI to wait for indication of core
idle before the SCI resumes activity.
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Unlock
1 Lock
0 Disable
1 Enable
0 No Action
1 Wait for Idle
ADSP-SC58x SEC Register Descriptions
2
1
0
0
0
0
EN (R/W)
Enable
17
16
0
0
0
NMIEN (R/W)
NMI Enable
register is read only.
SEC_CCTL[n]
7–25
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