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12 One-Time Programmable Memory Con-
troller (OTPC)
This chapter describes the operation of the OTP controller. The OTP module is a complete system integrating an
OTP memory core with a programming controller, charge pump, and voltage regulator. A built-in Hamming Code
Error Correction (ECC), and a fully implemented double-redundant program or read scheme protect the OTP data.
OTP memory access is through the
OTP memory does not support burst transfers, which are required to support cache line fills. As such,
CAUTION:
OTP memory should not be made cacheable. If it is, the OTP controller returns an error when a read
access is attempted.
OTPC Features
The OTP memory and controller have the following features:
• Built-in redundant read mode
• Built-in integrated power supply
• Built-in Hamming Code Error Correction (ECC)
• Full word serial (single bit at a time) programming with internal VPP
Error Correction
The OTP memory features a Hamming error correction implementation. Signal bit errors are automatically correc-
ted, and dual-bit errors are detected. Refer to
ECC is always enabled. ECC applies to each 16-bit segment. Because of this functionality, each 16-bit location can
only be written to once. Writing to a 16-bit location a second time results in unexpected behavior.
OTP Layout
This section details the memory layout of the OTP memory.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
OTP API Overview
provided by the ROM.
OTPC Interrupt
One-Time Programmable Memory Controller (OTPC)
Signals.
12–1
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