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TRU Architectural Concepts
The TRU supports a simple trigger-in/trigger-out model for modules that comply with the triggering functional
model. The TRU is the controller of the trigger system. Trigger outputs from trigger masters are mapped to trigger
inputs of trigger slaves through a set of programmable registers (TRU_SSR[n]).
System modules are trigger master only, trigger slave only, or trigger master and trigger slave.
All of the trigger input and output signals are connected to a trigger routing unit (TRU) which manages the connec-
tions of triggers between modules.
In multi-processor systems, multiple TRU units are provided. These TRUs are networked together. Generic Trigger
Ports (GTPs) are provided to forward trigger events from one TRU unit to another, forming a pathway from trigger
masters to trigger slaves wherever they might lie in the system.
TRU Programming Model
Implementing sequence control using the TRU requires, at a minimum, proper configuration of a trigger slave, a
trigger master, and the TRU module itself. The only requirement for the configuration procedure is that the trigger
master is configured and enabled as the last step.
Complete the following other steps:
• Configure the trigger slave for response to triggers.
• Configure the TRU to map the trigger master to the trigger slave through the
• Configure the trigger master to generate trigger assertions.
• Alternatively, use software triggering for trigger assertion. Writing the trigger master ID to the MTR register
generates software triggers.
Programming Concepts
The following concepts aid in programming the TRU.
• Trigger Sequence Configuration. A simple sequence consists of one trigger master and one trigger slave. More
complex trigger sequences consist of several trigger slaves functioning as trigger slave and trigger master. Addi-
tionally, trigger sequences can loopback to the original master forming a perpetual sequence.
• Software Triggering. Writing a trigger master ID to the MTR generates a trigger within the TRU from the
trigger master ID specified.
• Synchronization. The TRU can be used to coarsely synchronize events by mapping multiple trigger slaves to
the same trigger master or by generating multiple trigger master assertions simultaneously through the MTR.
• Configuration Protection. The TRU_SSR[n].LOCK bit and the TRU_GCTL.LOCK bit enable register level
write-protection when the global lock is asserted in the SPU.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
TRU Architectural Concepts
registers.
TRU_SSR[n]
8–13
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