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Interrupt Address Register
The
register indicates an attempt to make a read or write access to unimplemented addresses or ac-
SMPU_IADDR
cesses are non-aligned. The SMPU issues a bus error for this condition.
Figure 13-7: SMPU_IADDR Register Diagram
Table 13-11: SMPU_IADDR Register Fields
Bit No.
(Access)
31:0
VALUE
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
0
0
VALUE[15:0] (R)
Interrupt Address
31
30
0
0
VALUE[31:16] (R)
Interrupt Address
Bit Name
Interrupt Address.
The SMPU_IADDR.VALUE bit field is the address where an attempt to access an un-
implemented address or a non-aligned access has occurred.
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x SMPU Register Descriptions
5
4
3
2
1
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
13–21
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