Analog Devices ADSP-2106x SHARC Processor Manuals

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Analog Devices ADSP-2106x SHARC User Manual

Analog Devices ADSP-2106x SHARC User Manual (698 pages)

Brand: Analog Devices | Category: Computer Hardware | Size: 1 MB

Table of Contents

Table of Contents
3
Chapter 1 Introduction

25
CHAPTER 2 Computation Units

32
- Data Register File
  32
- Program Sequencer & Data Address Generators
  33
- Instruction Cache
  34
- Interrupts
  34
- Timer
  34
- Core Processor Buses
  34
- Internal Data Transfers
  35
- Context Switching
  35
- Instruction Set
  36
- Dual-Ported Internal Memory
  36
- External Memory & Peripherals Interface
  37
- Host Processor Interface
  37
- Multiprocessing
  38
- I/O Processor
  38
- Serial Ports
  38
- Link Ports
  39
- DMA Controller
  39
- Booting
  40
- Development Tools
  40
- Figure 1.4 System Design and Development Process
  41
- Mesh Multiprocessing
  42
- Additional Literature
  42
Computation Units

43
- Overview
  43
- Ieee Floating-Point Operations
  44
- Extended Floating-Point Precision
  45
- Short Word Floating-Point Format
  45
- Floating-Point Exceptions
  46
- Fixed-Point Operations
  46
- Rounding
  46
- Alu
  47
- ALU Operation
  48
- ALU Operating Modes
  48
- Saturation Mode
  49
- Floating-Point Rounding Modes
  49
- Floating-Point Rounding Boundary
  49
- ALU Status Flags
  49
- ALU Zero Flag (AZ)
  50
- ALU Underflow Flag (AZ, AUS)
  50
- ALU Negative Flag (AN)
  50
- ALU Overflow Flag (AV, AOS, AVS)
  50
- ALU Fixed-Point Carry Flag (AC)
  51
- ALU Sign Flag (AS)
  51
- ALU Invalid Flag (AI)
  51
- ALU Floating-Point Flag (AF)
  51
- Compare Accumulation
  51
- ALU Instruction Summary
  52
- Multiplier
  53
- Multiplier Operation
  53
- Fixed-Point Results
  54
- MR Registers
  54
- Fixed-Point Operations
  55
- Clear MR Register
  55
- Round MR Register
  56
- Saturate MR Register on Overflow
  56
- Floating-Point Operating Modes
  57
- Floating-Point Rounding Modes
  57
- Floating-Point Rounding Boundary
  57
- Multiplier Status Flags
  57
- Multiplier Underflow Flag (MU)
  58
- Multiplier Negative Flag (MN)
  59
- Multiplier Overflow Flag (MV)
  59
- Multiplier Invalid Flag (MI)
  59
- Multiplier Instruction Summary
  60
- Shifter
  61
- Shifter Operation
  61
- Bit Field Deposit & Extract Instructions
  62
- Shifter Status Flags
  66
- Shifter Zero Flag (SZ)
  66
- Shifter Overflow Flag (SV)
  66
- Shifter Sign Flag (SS)
  66
- Shifter Instruction Summary
  67
- Multifunction Computations
  68
- Register File
  69
- Alternate (Secondary) Registers
  70
Chapter 3 Program Sequencing

73
- Overview
  73
- Instruction Cycle
  74
  - Program Flow Variations
    74
- Program Sequencer Architecture
  75
  - Pipelined Execution Cycles
    75
- Figure 3.3 Program Sequencer Block Diagram
  76
- Program Sequencer Registers & System Registers
  77
- Program Sequencer Operations
  78
- Sequential Instruction Flow
  78
- Program Memory Data Accesses
  78
- Branches
  78
- Loops
  78
- Conditional Instruction Execution
  79
- Table 3.2 Condition & Loop Termination Codes
  80
- Branches (Call, Jump, Rts, Rti)
  81
- Delayed & Nondelayed Branches
  82
  - Nondelayed Branches
    82
- Figure 3.5 Delayed Branches
  83
- PC Stack
  84
- Loops (Do Until)
  85
- Restrictions & Short Loops
  86
- General Restrictions
  86
- Counter-Based Loops
  87
- Non-Counter-Based Loops
  88
  - One-Instruction Counter-Based Loops
    88
- Figure 3.8 Two-Instruction Counter-Based Loops
  89
- Loop Address Stack
  90
- Loop Counters and Stack
  91
- Curlcntr
  91
- Lcntr
  92
  - Pushing the Loop Counter Stack for Nested Loops
    92
- Interrupts
  93
- Interrupt Latency
  94
- Figure 3.10 Interrupt Handling
  95
- Interrupt Vector Table
  96
- Table 3.3 Interrupt Vectors & Priority
  97
- Interrupt Latch Register (IRPTL)
  98
- Interrupt Priority
  99
- Interrupt Masking & Control
  99
- Interrupt Mask Register (IMASK)
  99
- Interrupt Nesting & IMASKP
  100
- Status Stack Save & Restore
  101
- Software Interrupts
  101
- Clearing the Current Interrupt for Reuse
  102
- External Interrupt Timing & Sensitivity
  103
- Asynchronous External Interrupts
  104
- Multiprocessor Vector Interrupts (VIRPT)
  104
- Timer
  105
- Timer Enable/Disable
  106
- Timer Interrupts
  107
- Timer Registers
  108
- Stack Flags
  108
- Idle & Idle16
  109
- Instruction Cache
  110
- Cache Architecture
  110
- Cache Efficiency
  111
- Figure 3.16 Cache-Inefficient Code
  112
- Cache Disable & Cache Freeze
  113
- Adsp-2106X Architecture
  32
- Core Processor
  32
Chapter 4 Data Addressing

115
- Overview
  115
- Dag Registers
  115
- Figure 4.1 Data Address Generator Block Diagram
  116
- Alternate DAG Registers
  117
- Dag Operation
  118
- Address Output & Modification
  118
- DAG Modify Instructions
  119
- Immediate Modifiers
  120
- Circular Buffer Addressing
  120
- Circular Buffer Operation
  121
  - Circular Data Buffers
    121
- Circular Buffer Registers
  122
- Circular Buffer Overflow Interrupts
  122
- Bit-Reversal
  124
- Bit-Reverse Mode
  124
- Bit-Reverse Instruction
  124
- Dag Register Transfers
  125
- DAG Register Transfer Restrictions
  126
Chapter 5 Memory

127
Chapter 6 Dma

183
- DMA Controller Features
  183
- Setting up DMA Transfers
  184
- Dma Control Registers
  185
- Serial Port DMA Control
  192
- Link Port DMA Control
  193
- Table 6.8 LCTL Control Bits for Link Port DMA
  194
- Port Selection for Shared DMA Channels
  195
- DMA Channel Status Register (DMASTAT)
  196
- Table 6.10 DMASTAT Register
  197
- Dma Controller Operation
  198
- DMA Channel Parameter Registers
  199
  - Table 6.11 DMA Parameter Registers
    201
  - Internal Request & Grant
    202
- DMA Channel Prioritization
  203
- Rotating Priority for Ext. Port Channels
  204
- Figure 6.5 Rotating Priority Example (ADSP-21060 & ADSP-21062)
  205
- DMA Chaining
  206
- Chain Insertion
  210
- DMA Interrupts
  211
  - Starting & Stopping DMA Sequences
    213
  - External Port Dma
    214
- Packing Status
  216
- Master Mode
  218
- Handshake Mode
  220
- Figure 6.8 DMA Handshake Timing with Asynchronous Requests
  223
- External Handshake Mode
  224
- System Configurations for ADSP-2106X Interprocessor DMA
  225
- Dma Throughput
  226
  - Figure 6.10 System Configurations for ADSP-2106X-To-ADSP-2106X DMA
    227
  - Figure 6.11 Example DMA Hardware Interface
    228
- Two-Dimensional Dma
  230
- D DMA Operation
  231
  - Overview
    233
  - Figure 7.1 ADSP-2106X Multiprocessor System
    234
Chapter 7 Multiprocessing

236
- Multiprocessing System Architectures
  236
  - Cluster Multiprocessing
    237
- Link Port Data Transfers in a Cluster
  239
- SIMD Multiprocessing
  240
- Multiprocessor Bus Arbitration
  241
- Bus Arbitration Protocol
  242
  - Figure 7.5 Bus Arbitration Timing
    244
  - Figure 7.6 Bus Request & Read/Write Timing
    245
- Bus Arbitration Priority (RPBA)
  246
- Bus Mastership Timeout
  247
  - Core Priority Access
    248
- Figure 7.7 Core Priority Access Timing
  250
- Bus Synchronization after Reset
  251
- Slave Direct Reads & Writes
  253
- Direct Writes
  254
- Direct Reads
  255
- DMA Transfers
  260
- DMA Transfers to External Memory
  261
- Example: Sharing a DMA Channel with Reflective Semaphores
  263
- Interprocessor Messages & Vector Interrupts
  264
- Vector Interrupts (VIRPT)
  265
  - Systat Register Status Bits
    266
  - Figure 7.9 SYSTAT Register
    267
  - Overview
    269
  - Figure 8.1 External Port & Host Interface
    270
  - Table 8.1 Host Interface Signals
    271
Chapter 8 Host Interface

273
- Host Processor Control of the Adsp-2106X
  273
- Acquiring the Bus
  274
- Figure 8.2 Example Timing for Bus Acquisition
  275
- Asynchronous Transfers
  276
- Asynchronous Transfer Timing
  278
- Figure 8.3 Example Timing for Host Read & Write Cycles
  279
- Synchronous Transfers
  280
- Host Interface Deadlock Resolution with SBTS
  281
- Direct Writes
  282
- Direct Reads
  283
- Shadow Write FIFO
  285
- Data Transfers through the Epbx Buffers
  286
- Interrupts for Single-Word Transfers
  287
- DMA Transfers
  288
- DMA Transfers to External Memory
  289
- Figure 8.4 SYSCON Register
  290
- Data Bus Lines Used for Different Packing Modes
  293
- Bit Data Packing
  294
- Figure 8.5 Example Timing for Host Interface Data Packing
  295
- Bit Instruction Packing
  296
- Systat Register Status Bits
  297
  - Figure 8.6 SYSTAT Register
    298
  - Interprocessor Messages & Vector Interrupts
    299
- Message Passing (Msgrx)
  300
- Host Vector Interrupts (VIRPT)
  301
- System Bus Interfacing
  302
- Deadlock Resolution
  306
- ADSP-2106X DMA Access to System Bus
  307
- Multiprocessing with Local Memory
  308
- ADSP-2106X to Microprocessor Interface
  309
Appendix C Numeric Formats

311
Appendix D Jtag Test Access Port

311
- Overview
  311
Chapter 9 Link Ports

312
- Link Port to Link Buffer Assignment
  312
  - Figure 9.B Link Port Communication Examples
    313
  - Link Port DMA Channels
    314
- Link Port Interrupts
  315
- Link Buffer Control Register (LCTL)
  316
  - Figure 9.2 LCTL Register
    318
  - Link Common Control Register (LCOM)
    319
  - Figure 9.3 LCOM Register
    321
  - Link Assignment Register (LAR)
    322
- Handshake Control Signals
  323
- Figure 9.5 Link Port Handshake Timing
  324
- Link Buffers
  325
- Core Processor Access to Link Buffers
  326
- DMA Chaining for Link Ports
  328
- Link Port Interrupts with DMA Enabled
  329
- Transmission Error Detection
  333
- Figure 9.7 Token Passing Flow Chart
  334
- Link Transmission Lines
  336
- System Design Example: Local Dram Interface
  337
- Programming Examples
  338
  - Listing 9.2 DMA Transfer Example
    340
  - Listing 9.3 Link Token Passing Example
    341
Appendix E Control/Status Registers

357
- Overview
  357
Chapter 10 Serial Ports

371
- Maximum Clock Rate Restrictions
  371
- Data Word Formats
  372
- Data Type
  373
- Companding
  374
- Clock Signal Options
  375
- Frame Sync Options
  376
- Internal Vs. External Frame Syncs
  377
- Active Low Vs. Active High Frame Syncs
  378
- Early Vs. Late Frame Syncs
  379
- Data-Independent Transmit Frame Sync
  380
  - Multichannel Operation
    381
- Frame Syncs in Multichannel Mode
  382
- Multichannel Control Bits in STCTL, SRCTL
  383
- Multichannel Frame Delay
  384
- SPORT Receive Comparison Registers
  385
- Serial Ports
  386
- Transferring Data between Sports and Memory
  387
- DMA Block Transfers
  388
- SPORT DMA Channel Setup
  389
- Table 10.8 Parameter Registers for each SPORT DMA Channel
  390
- SPORT DMA Chaining
  391
- Single-Word Transfers
  392
- Sport Pin Driver Concerns
  393
- Listing 10.1 Non-Interrupt-Driven SPORT Control (Single-Word Transfers)
  394
- Single-Word Transfers with Interrupts
  395
- Listing 10.2 Interrupt-Driven SPORT Control (Single-Word Transfers)
  396
- DMA Transfers with Interrupts
  397
  - Listing 10.3 SPORT DMA Example
    398
  - Overview
    399
Chapter 11 System Design

400
- Pin Definitions
  400
- Pin States at Reset
  407
- Reset & Clkin
  408
- Input Synchronization Delay
  409
- Flag Inputs
  410
- Flag Outputs
  411
- Ez-Ice Emulator
  412
- Figure 11.4 JTAG Scan Path Connections for Multiprocessor ADSP-2106X Systems
  414
- Input Signal Conditioning
  415
- High Frequency Design Considerations
  416
  - Clock Specifications & Jitter
    417
  - Point-To-Point Connections
    419
- Signal Integrity
  420
- Oscilloscope Probes
  424
  - Booting
    425
  - Table 11.2 Boot Mode Selection Pins
    426
- EPROM Booting
  427
  - For EPROM Booting
    428
- Loading the Remaining EPROM Data
  429
- Writing to BMS Memory Space
  430
- Table 11.4 Ext. Port DMA Channel 6 Parameter Register Initialization for Host Booting
  431
- Link Port Booting
  432
- Multiprocessor Booting
  433
  - Processors-Take-Turns
    434
- Multiprocessor Link Port Booting
  435
- Important Programming Reminders
  436
- Program Memory Data Access in Loops
  437
- One- & Two-Instruction Loops
  438
- Circular Buffer Initialization
  439
- Two Writes to Register File
  440
  - Mixing 32-Bit & 48-Bit Words in a Memory Block
    441
  - Data Delays, Latencies, & Throughput
    442
  - Table 11.5 Data Delays & Throughputs
    444
  - Table 11.6 Latencies & Throughputs
    445
  - A.1 Overview
    447
  - A.2 Instruction Set Summary
    448
  - A.3 Opcode Notation
    454
  - A.4 Universal Register Codes
    458
Appendix A Instruction Set Reference

461
- Group I. Compute and Move Instructions
  461
- Compute / Dreg÷DM / Dreg÷Pm
  462
Compute

463
- Compute / Ureg÷DM|Pm , Register Modify
  464
- Compute / Dreg÷DM|Pm , Immediate Modify
  466
- Compute / Ureg÷Ureg
  468
- Immediate Shift / Dreg÷DM|Pm
  470
- Compute / Modify
  472
- Group II. Program Flow Control
  473
  - Direct Jump|Call
    474
  - Indirect Jump|Call / Compute
    476
  - Indirect Jump or Compute / Dreg÷DM
    478
  - Return from Subroutine|Interrupt / Compute
    480
  - Do until Counter Expired
    482
  - Do until
    484
- Group III. Immediate Move
  485
  - Ureg÷DM|Pm (Direct Addressing)
    486
  - Ureg÷DM|Pm (Indirect Addressing)
    487
  - Immediate Data ' DM|PM
    488
- Group IV. Miscellaneous
  491
  - System Register Bit Manipulation
    492
  - I Register Modify / Bit-Reverse
    494
  - Push|Pop Stacks /Flush Cache
    496
  - Idle
    498
  - Idle16
    499
  - Cjump / Rframe
    500
    
    B.1 Overview
    503
    
    B.2.1 ALU Operations
    504
    
    Table B.2 Floating-Point ALU Operations
    505
Appendix B Compute Operation Reference

511
- Comp(Rx, Ry)
  511
- Rn = –Rx
  516
- Rn = MIN(Rx, Ry)
  523
- Rn = MAX(Rx, Ry)
  524
- Comp(Fx, Fy)
  531
- Fn = –Fx
  532
- Fn = RECIPS Fx
  541
- Fn = RSQRTS Fx
  542
- Fn = Fx COPYSIGN Fy
  543
- Fn = MIN(Fx, Fy)
  544
- Fn = MAX(Fx, Fy)
  545
  - B.2.2 Multiplier Operations
    547
  - Table B.4 Multiplier Mod2 Options
    548
- Rn|Mr = SAT MR
  552
- Rn|Mr = RND MR
  553
- Mr=Rn / Rn=Mr
  554
  - B.2.3 Shifter Operations
    556
  - Rn = LSHIFT Rx by Ry|<Data8>
    557
  - Rn = Rn or LSHIFT Rx by Ry|<Data8>
    558
  - Rn = ASHIFT Rx by Ry|<Data8>
    559
  - Rn = Rn or ASHIFT Rx by Ry|<Data8>
    560
  - Rn = ROT Rx by Ry|<Data8>
    561
  - Rn = BCLR Rx by Ry|<Data8>
    562
  - Rn = BSET Rx by Ry|<Data8>
    563
  - Rn = BTGL Rx by Ry|<Data8>
    564
  - BTST Rx by Ry|<Data8>
    565
  - Rn = FDEP Rx by Ry|<Bit6>:<Len6>
    566
  - Rn = Rn or FDEP Rx by Ry|<Bit6>:<Len6>
    567
  - Rn = FDEP Rx by Ry|<Bit6>:<Len6> (SE)
    568
  - Rn = Rn or FDEP Rx by Ry|<Bit6>:<Len6> (SE)
    569
  - Rn = FEXT Rx by Ry|<Bit6>:<Len6>
    570
  - Rn = FEXT Rx by Ry|<Bit6>:<Len6> (SE)
    571
- Fn = FUNPACK Rx
  577
  - B.3 Multifunction Computations
    578
  - Dual Add/Subtract (Fixed-Pt.)
    579
  - Dual Add/Subtract (Floating-Pt)
    580
    
    Parallel Multiplier & ALU (Fixed-Pt.)
    581
    
    Parallel Multiplier & ALU (Floating-Pt.)
    582
    
    Table B.7 Parallel Multiplier/Alu Computations
    583
    
    Parallel Multiplier & Dual Add/Subtract
    584
    
    C.1 Overview
    587
    
    C.3 Extended Precision Floating-Point Format
    588
    
    C.4 Short Word Floating-Point Format
    589
    
    C.5 Fixed-Point Formats
    591
    
    Figure C.4 32-Bit Fixed-Point Formats
    592
    
    Figure C.5 64-Bit Unsigned Fixed-Point Product
    593
    
    Figure C.6 64-Bit Signed Fixed-Point Product
    594
    
    D.1 Overview
    595
    
    D.2 Test Access Port
    596
    
    D.3 Instruction Register
    597
    
    Figure D.1 Serial Scan Paths
    598
    
    D.4 Boundary Register
    599
    
    D.5 Device Identification Register
    607
    
    E.1 Overview
    609
    
    E.2 System Registers (Core Processor)
    610
    
    E.2.2 System Register Bit Operations
    611
    
    E.3 Iop Registers (I/O Processor)
    612
    
    Table E.3 IOP Registers (System Control)
    613
    
    Table E.4 IOP Registers (DMA)
    614
    
    Table E.5 IOP Registers (Link Ports)
    615
    
    E.3.2 IOP Register Access Restrictions
    616
    
    E.3.4 IOP Register Write Latencies
    617
    
    Table E.7 IOP Register Addresses, RESET Initialization, & Grouping
    619
    
    E.4 Mode1 Register
    622
    
    E.5 Mode2 Register
    624
    
    E.7 Sticky Status (Stky)
    628
    
    E.8 Interrupt Latch (Irptl) & Interrupt Mask Imask)
    630
    
    E.9 System Configuration (Syscon)
    632
    
    E.10 System Status (Systat)
    637
    
    E.13 Dma Channel Status (Dmastat)
    647
    
    E.14 Link Buffer Control (Lctl)
    649
    
    E.15 Link Buffer Common Control (Lcom)
    651
    
    E.16 Link Assignment Register (Lar)
    654
    
    E.17 Link Service Request (Lsrq)
    655
    
    E.19 Sport Receive Control (Srctl0, Srctl1)
    659
    
    E.20 Sport Divisors (Tdiv, Rdiv)
    661
    
    E.21 Symbol Definitions File (Def21060.H)
    662
    
    Interrupt Vector Addresses
    669

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