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ADSP-SC58x L2CTL Register Descriptions
Error Type 0 Address Register
The
L2CTL_EADDR0
This register is be updated only if the corresponding error status bit (L2CTL_STAT.ERR0) is cleared. After the
status bit is set for an error, further errors do not update the
sponding status bit. If read and write access errors occur simultaneously, the register captures the write access error
address.
Figure 9-6: L2CTL_EADDR0 Register Diagram
Table 9-7: L2CTL_EADDR0 Register Fields
Bit No.
(Access)
31:0
VALUE
(R/NW)
9–16
register holds the address that created an access error on the L2 port 0 bus interface (cores).
15
14
0
0
VALUE[15:0] (R)
ERRADDR Value
31
30
0
0
VALUE[31:16] (R)
ERRADDR Value
Bit Name
ERRADDR Value.
The L2CTL_EADDR0.VALUE bits hold the address causing the bus error.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
L2CTL_EADDR0
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
1
0
0
0
0
0
0
0
Description/Enumeration
register until a W1C clears the corre-
5
4
3
2
1
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
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