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Left-Justified Mode .......................................................................................................................... 34–30
Right-Justified Mode........................................................................................................................ 34–31
Multichannel (TDM) Mode ................................................................................................................ 34–33
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S Mode................................................................................................................................. 34–36
Gated Clock Mode .............................................................................................................................. 34–37
Data Transfers and Interrupts .................................................................................................................... 34–38
Data Buffers ........................................................................................................................................... 34–38
Data Buffer Status ............................................................................................................................... 34–40
Single-Word (Core) Transfers ................................................................................................................. 34–40
DMA Transfers....................................................................................................................................... 34–41
Data Transfer Interrupt .......................................................................................................................... 34–42
Error Detection (Status) Interrupt .......................................................................................................... 34–43
SPORT Programming Model .................................................................................................................... 34–44
Initializing Core-Driven (Non-MCM) Transfers..................................................................................... 34–45
Initializing Multichannel Transfers ......................................................................................................... 34–46
Using DMA for SPORT Transfers.......................................................................................................... 34–47
Using Companding as a Function........................................................................................................... 34–47
ADSP-SC58x SPORT Register Descriptions ............................................................................................ 34–48
Half SPORT 'A' Multichannel 0-31 Select Register .............................................................................. 34–50
Half SPORT 'B' Multichannel 0-31 Select Register .............................................................................. 34–51
Half SPORT 'A' Multichannel 32-63 Select Register ............................................................................ 34–52
Half SPORT 'B' Multichannel 32-63 Select Register ............................................................................ 34–53
Half SPORT 'A' Multichannel 64-95 Select Register ............................................................................ 34–54
Half SPORT 'B' Multichannel 64-95 Select Register ............................................................................ 34–55
Half SPORT 'A' Multichannel 96-127 Select Register .......................................................................... 34–56
Half SPORT 'B' Multichannel 96-127 Select Register .......................................................................... 34–57
Half SPORT 'A' Control 2 Register ...................................................................................................... 34–58
Half SPORT 'B' Control 2 Register ...................................................................................................... 34–59
Half SPORT 'A' Control Register ......................................................................................................... 34–60
Half SPORT 'B' Control Register ......................................................................................................... 34–68
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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