Table of Contents
Advertisement
DPM Event Control
The DPM event is triggered when an enabled wake-up is asserted. The DPM generates bus errors when a misaligned
access to a register occurs. It also generates errors when an attempt is made to access unused DPM address space or a
write-protected register.
DPM Events
The DPM event interrupt is triggered when any bit in the
wake-up was asserted. The DPM event interrupt stays active until the user clears any bits that are set in the
register.
DPM_STAT
DPM Errors
The DPM generates a bus error when a read or write transaction is attempted to an unused address within the DPM
address range. It also generates a bus error when a misaligned access is made to a DPM register. In addition to the
bus error, the DPM sets the DPM_STAT.ADDRERR bit.
If a write to a write-protected DPM register is attempted, the DPM generates a bus error. In addition, the DPM sets
the DPM_STAT.LWERR bit.
DPM Programming Model
The DPM_PER_DIS0 Register Mapping table shows the module clocks and the corresponding peripheral. The
DPM_PER_DIS0
register is used to shut off the clock to each peripheral if it is not required by the application.
NOTE:
In the table, SMPU-L2CTL-CL2_x and SMPU-L2CTL-DL2_x correspond to the SMPU modules associ-
ated with the core and the DMA ports of L2 respectively. The six instances of SMPU blocks are shown in
the
Figure 9-1 ADSP-SC58x Complete L2 System Block Diagram
for the port 0-core and another for the port 1-DMA.
Table 5-2: DPM_PER_DIS0 Register Mapping
Peripheral Name
FIR0
IIR0
FFT0
RTC0
DAI0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DPM_STAT
Gated Module clocks
SCLK0
SCLK0
SYSCLK
SCLK0
SCLK0
CLK05
SYSCLK
register is set, indicating that an enabled
– two SMPUs for each L2CLTL, one
DPM_PER_DIS0 bit
0
1
2
4
5
DPM Event Control
5–3
Advertisement
Table of Contents
