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1. The SEC compares the
in the
SEC_CPND[n]
2. The SEC copies
SEC_CPND[n]
3. The core reads the
4. The core writes to the
5. The SEC deasserts the INT signal and clears the SEC_SSTAT[n].PND bit and sets the
SEC_SSTAT[n].ACT bit of the source (A) going active.
6. The SEC compares the
SEC_CACT[n]
(A) register value is a higher priority, continue.
7. The SEC copies the
signal.
8. The core reads the
9. The core writes to the
10. The SEC deasserts the INT signal and clears the SEC_SSTAT[n].PND bit and sets the
SEC_SSTAT[n].ACT bit of the source (B) going active.
11. The core writes the
12. The SEC clears the SEC_SSTAT[n].ACT bit of the source (B) being ended.
13. The core writes the
14. The SEC clears the SEC_SSTAT[n].ACT bit of the source (A) being ended.
System Interrupt Priorities
Each system interrupt source has its own programmable priority level which is configured using the
SEC_SCTL[n].PRIO bit field. The SCI evaluates the priority of all pending sources to determine the source of
the highest-priority pending system interrupt for forwarding to the attached core. If more than one source of the
pending system interrupt has the same priority setting, the SCI chooses the one with the lowest SID. For example, if
SID 0, SID 1, and SID 2 are all pending and have the same priority setting, the SCI chooses SID 0 as the highest-
priority source.
SEC Error
The processor includes an SEC error (SEC_GSTAT.ERR) as a source input to the SEC to allow for handling the
error as an interrupt or fault.
SEC Programming Model
Implementing a system interrupt service model using the SEC requires, at a minimum:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SEC_CPND[n]
(A) register value to the
register is a higher priority, continue.
(A) register to the
SEC_CSID[n]
(A) register (or core version).
SEC_CSID[n]
register (or core version, asserts the acknowledge signal).
SEC_CPND[n]
(B) register value to the
(B) register value to
SEC_CPND[n]
(B) register (or core version).
SEC_CSID[n]
SEC_CSID[n]
register (or core version, asserts the acknowledge signal).
of the active interrupt (B) to the
SEC_CSID[n]
SEC_CSID[n]
of the active interrupt (A) to the
SEC_CACT[n]
register and asserts the interrupt signal.
SEC_CSID[n]
SEC_CACT[n]
SEC_CSID[n]
SEC_END
SEC_END
SEC Architectural Concepts
register and if the interrupt
(A) register value. If the
register and asserts the interrupt
register.
register.
7–17
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