Analog Devices ADSP-SC58 Series Hardware Reference Manual page 647

Table 14-28: PINT_EDGE_CLR Register Fields (Continued)
Bit No.
(Access)
15 PIQ15
(R/W1C)
14 PIQ14
(R/W1C)
13 PIQ13
(R/W1C)
12 PIQ12
(R/W1C)
11 PIQ11
(R/W1C)
10 PIQ10
(R/W1C)
9 PIQ9
(R/W1C)
8 PIQ8
(R/W1C)
7 PIQ7
(R/W1C)
6 PIQ6
(R/W1C)
5 PIQ5
(R/W1C)
4 PIQ4
(R/W1C)
3 PIQ3
(R/W1C)
2 PIQ2
(R/W1C)
1 PIQ1
(R/W1C)
0 PIQ0
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Pin Interrupt 15 Level.
Set the PINT_EDGE_CLR.PIQ15 bit to enable level sensitivity.
Pin Interrupt 14 Level.
Set the PINT_EDGE_CLR.PIQ14 bit to enable level sensitivity.
Pin Interrupt 13 Level.
Set the PINT_EDGE_CLR.PIQ13 bit to enable level sensitivity.
Pin Interrupt 12 Level.
Set the PINT_EDGE_CLR.PIQ12 bit to enable level sensitivity.
Pin Interrupt 11 Level.
Set the PINT_EDGE_CLR.PIQ11 bit to enable level sensitivity.
Pin Interrupt 10 Level.
Set the PINT_EDGE_CLR.PIQ10 bit to enable level sensitivity.
Pin Interrupt 9 Level.
Set the PINT_EDGE_CLR.PIQ9 bit to enable level sensitivity.
Pin Interrupt 8 Level.
Set the PINT_EDGE_CLR.PIQ8 bit to enable level sensitivity.
Pin Interrupt 7 Level.
Set the PINT_EDGE_CLR.PIQ7 bit to enable level sensitivity.
Pin Interrupt 6 Level.
Set the PINT_EDGE_CLR.PIQ6 bit to enable level sensitivity.
Pin Interrupt 5 Level.
Set the PINT_EDGE_CLR.PIQ5 bit to enable level sensitivity.
Pin Interrupt 4 Level.
Set the PINT_EDGE_CLR.PIQ4 bit to enable level sensitivity.
Pin Interrupt 3 Level.
Set the PINT_EDGE_CLR.PIQ3 bit to enable level sensitivity.
Pin Interrupt 2 Level.
Set the PINT_EDGE_CLR.PIQ2 bit to enable level sensitivity.
Pin Interrupt 1 Level.
Set the PINT_EDGE_CLR.PIQ1 bit to enable level sensitivity.
Pin Interrupt 0 Level.
Set the PINT_EDGE_CLR.PIQ0 bit to enable level sensitivity.
ADSP-SC58x PINT Register Descriptions
Description/Enumeration
14–75