Analog Devices ADSP-SC58 Series Hardware Reference Manual page 780

ADSP-SC58x SPI Register Descriptions
Table 16-33: SPI_STAT Register Fields (Continued)
Bit No.
(Access)
7 MF
(R/W1C)
6 TC
(R/W1C)
5 TUR
(R/W1C)
4 ROR
(R/W1C)
2 TUWM
(R/NW)
1 RUWM
(R/NW)
16–74
Bit Name
Mode Fault Indication.
The SPI_STAT.MF bit, when SPI is a master and SPI_CTL.PSSE is enabled, in-
dicates that multiple masters have asserted slave select inputs.
Transmit Collision Indication.
The SPI_STAT.TC bit, when SPI is a slave, indicates that the load of data into the
shift register has occurred too close to the first transmitting edge of the SPI clock.
Transmit Underrun Indication.
The SPI_STAT.TUR bit, when the transmit FIFO (SPI_TFIFO) is empty, indi-
cates that the last word in the transmit FIFO has been re-sent as transmit data. Alter-
nately, it indicates that zero has been sent as transmit data.
Receive Overrun Indication.
The SPI_STAT.ROR bit, when the receive FIFO (SPI_RFIFO) is full, indicates
that a word in the receive FIFO has been overwritten with incoming receive data. Al-
ternately, it indicates that incoming receive data has been discarded.
Transmit Urgent Watermark Breached.
The SPI_STAT.TUWM bit indicates that the transmit urgent watermark
(SPI_TXCTL.TUWM) has been reached. This condition is cleared when the transmit
FIFO fills enough to reach the transmit regular watermark (SPI_TXCTL.TRWM).
Receive Urgent Watermark Breached.
The SPI_STAT.RUWM bit indicates that the receive urgent watermark
(SPI_RXCTL.RUWM) has been reached. This condition is cleared when the receive
FIFO empties enough to reach the receive regular watermark (SPI_RXCTL.RRWM).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No status
1 Mode fault occurred
0 No status
1 Transmit collision occurred
0 No status
1 Transmit underrun occurred
0 No status
1 Receive overrun occurred
0 Tx regular watermark reached
1 Tx urgent watermark breached
0 Rx regular watermark reached
1 Rx urgent watermark breached