Table of Contents
Advertisement
SPI Interrupt Signals ................................................................................................................................. 16–28
Data Interrupts....................................................................................................................................... 16–28
Status Interrupts..................................................................................................................................... 16–29
Error Conditions .................................................................................................................................... 16–29
SPI Programming Concepts....................................................................................................................... 16–30
Master Operation in Non-DMA Modes ................................................................................................. 16–30
Slave Operation in Non-DMA Modes .................................................................................................... 16–31
Configuring DMA Master Mode............................................................................................................ 16–32
Configuring DMA Slave Mode Operation.............................................................................................. 16–33
ADSP-SC58x SPI Register Descriptions ................................................................................................... 16–34
Clock Rate Register ............................................................................................................................... 16–36
Control Register .................................................................................................................................... 16–37
Delay Register ....................................................................................................................................... 16–43
Masked Interrupt Condition Register .................................................................................................... 16–44
Masked Interrupt Clear Register ............................................................................................................ 16–46
Interrupt Mask Register ......................................................................................................................... 16–49
Interrupt Mask Clear Register ............................................................................................................... 16–51
Interrupt Mask Set Register ................................................................................................................... 16–54
Memory Mapped Read Header (Only on SPI2) ..................................................................................... 16–57
SPI Memory Top Address (Only on SPI2) ............................................................................................. 16–61
Receive FIFO Data Register ................................................................................................................... 16–62
Received Word Count Register .............................................................................................................. 16–63
Received Word Count Reload Register .................................................................................................. 16–64
Receive Control Register ........................................................................................................................ 16–65
Slave Select Register ............................................................................................................................... 16–68
Status Register ....................................................................................................................................... 16–71
Transmit FIFO Data Register ................................................................................................................ 16–76
Transmitted Word Count Register ......................................................................................................... 16–77
Transmitted Word Count Reload Register ............................................................................................. 16–78
Transmit Control Register ..................................................................................................................... 16–79
xxii
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Advertisement
Table of Contents
