Table of Contents
Advertisement
Channel B-Low Full Duty0 Register
The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The
register contains the PWM_BL_DUTY0.DUTY bit field from the
PWM_BL_DUTY0
PWM_BL_DUTY0.ENHDIV bit field from the
Note that the
PWM_BL_DUTY0
When heightened-precision edge placement is enabled, bits [15:8] of these registers form the decimal part of a non-
integer, fixed-point duty cycle value in Q15.8 format. The lowest bits are ignored.
Figure 19-52: PWM_BL_DUTY0 Register Diagram
Table 19-30: PWM_BL_DUTY0 Register Fields
Bit No.
(Access)
31:16
DUTY
(R/W)
15:14
ENHDIV
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_BL0_HP
register reads the
15
14
13
0
0
0
ENHDIV (R/W)
Enhanced Precision Divider Bits
31
30
29
0
0
0
DUTY (R/W)
Coarse Duty Value
Bit Name
Coarse Duty Value.
The PWM_BL_DUTY0.DUTY bits determine the output pulse-widths in the normal
PWM operation. When heightened-precision edge placement is enabled, the
PWM_BL_DUTY0.DUTY bit field forms the integer part of a non-integer, fixed-point
duty cycle value in Q15.8 format.
Enhanced Precision Divider Bits.
The PWM_BL_DUTY0.ENHDIV bits form the decimal part of a non-integer, fixed-
point duty cycle value when heightened-precision edge placement is enabled in Q15.8
format.
register.
PWM_BL0
and the
PWM_BL0_HP
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x PWM Register Descriptions
register and the
PWM_BL0
register values and visa-versa.
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
19–69
Advertisement
Table of Contents
